Hi,In my VIP chain, I have camera- CVI-II (progressive 1024x768)>>clipper-II>>Chroma resampler (output format 4:4:4 Filtered)>>Color Plane Sequencer>>Color Space Converter-II>>Scaler-II Edge Adaptive (Polyphase)>>Frame Buffer-II>>CVO -II(1024x768) all using 100MHz Other IPs are- clock Source, Nios-II processor, On chip Memory, JTAG UART, System ID peripheral, Interval Timer, Avalon ALTPLL, clock Bridge, 4 PIO, Avalon MM clock crossing bridge. This whole design was working fine and the image that was captured by camera was displayed on the HDMI output(1024 x768) –(computer monitor) – perfectly. We wanted to boot this design from flash, so the Quad SPI controller IP -uses clock 25Mhz was added and JTAG UART was removed. (as per Altera tech support’s recommendation) Since then, the image that is displayed on the monitor has flicker in it and the lower half of the image is misaligned with the upper part. If someone can give me solution to remove the flicker and misalignment in the image and get smooth image, I would sincerely appreciate that. I desperately need help in this regard as the project is in critical condition. Thank you. We are using DECA board, MAX10 FPGA and NIOS-2
Are you happy with your timing constraints?I wouldn't expect the fact you're booting from FLASH to be an issue - I'm concerned this is some misdirection and that the problem is elsewhere. Whilst the changes to the design you mention sound trivial enough, they'll change the routing, potentially significantly. If your Nios is booting from FLASH (I think it is, right? albeit with this new fault) then that should give you some confidence in that interface. If timing constraints are missing then you were potentially lucky with your original, functioning design. Cheers, Alex
Thanks Alex, Timing constraints are in place for the original design and I hope they are correct, For the new design after QSPI controller added, I have not changed any original timing constraints. May be adding and removing IP changed timing causing flicker. Besides, my original design was compiled using Quartus 15.0 and the new one is in Quartus 16.1. I am not sure where to start debugging, any suggestions are appreciated.Thanks. Yes, design is booting from QSPI flash but with this new problem.
Any progress on this? Some trivial thoughts following your last post...Depending on how you've connected up your QSPI controller and FLASH your timing constraints may need to change. However, if your design boots reliably from FLASH then it's likely there's no issue there. Yes, adding/changing IP will change the timing, and potentially change the timing across the entire design. However, you're simply interested in whether it meets timing. And this in turn relies on your timing constraints being accurate. Sorry I've nothing concrete to offer. However, my hunch remains there's a functional gremlin in there somewhere - which I'll struggle to help you with... Cheers, Alex
This sounds like it could be a start-up problem, like your image pipeline is not getting initialized or reset properly. I would focus on what changed with regard to pipeline startup after you changed your boot method.