Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21615 Discussions

ByteBlasterII JTAG chain problem detected

Altera_Forum
Honored Contributor II
1,922 Views

Hi 

I´m trying to program a EP3C5E144C8N FPGA in JTAG mode using a ByteBlasterII cable. The pins are connected as indicated in the JTAG configuration of a single device using a download cable (Fig 10.24 of the Cyclone III handbook). All the power suplies used have been measured in the device and are OK. 

When I test the JTAG chain integrity the QuartusII return the messages: 

-No device detected 

-The TDO connection to the dowload cable migth be shorted to GND or is an open circuit 

-The TCK and TMS connections to the last device migth have problem. 

 

I used the IDCODE iteration and tested all the signals in the blaster connector and the TDO signal is always in 0.01V when I think that this signal must change around 2.5V when programming. 

 

Any idea? 

Thank in advance
0 Kudos
11 Replies
Altera_Forum
Honored Contributor II
1,093 Views

The TDO signal should toggle during an integrity/infrastructure test since data is (should be) output from this line back to the 'blaster cable. 

 

IIRC doesn't the byteBlaster take power from teh JTAG header, if so you 

had better check you have power here too. 

 

KR 

 

Paul
0 Kudos
Altera_Forum
Honored Contributor II
1,093 Views

Hi 

 

I used an oscilloscope and when I press Start in the iteration test I see pulses in TCK, TDI and TMS pins, but not in TDO pin, wich is always in OV. 

One doubt: TDI is in high level before press START and TCK and TMS are in low levels, but TMS is pulled up to VCCA. It doesn´t mean that TMS initial level is bad? 

Thanks
0 Kudos
Altera_Forum
Honored Contributor II
1,093 Views

One of the suggestions at the top was.. 

 

'The TDO connection to the dowload cable migth be shorted to GND or is an open circuit' 

 

Did you try buzzing the TDO to GND to check if ther is a short. Is it actually 

adjacent to a GND pin on the pin-out ? 

 

TDO should give something out. 

 

KR 

 

Paul
0 Kudos
Altera_Forum
Honored Contributor II
1,093 Views

-Did you apply a VCCA of 2.5V for Cyclone III? 

-Did you connect the enhanced pad to GND?
0 Kudos
Altera_Forum
Honored Contributor II
1,093 Views

Hi Paul 

 

Thers´nt short betwen TDO and GND. There is 205 Kohms between both lines. 

Considering that I have signals in TCK, TMS and TDI, may I assume that my ByteBlasterII is ok? 

Is possible that my cicloneIII is damaged? 

 

Thanks for your reply 

 

Abel
0 Kudos
Altera_Forum
Honored Contributor II
1,092 Views

Hi 

 

Yes, I applied 2.5V to both VCCA pins in my cycloneIII, but I used the same GND for all the power supply (1.2V VCCINT, 2.5V VCCA and 3.3V VCCIO). I read some comments that in the cyclone III is not strictly necessary to isolate GNDA, is that correct? Instead I used ferrite bead and capacitors for each one. 

I had some problems to solder the GND to the enhanced pad. I´ll check it again. 

Thanks
0 Kudos
Altera_Forum
Honored Contributor II
1,093 Views

Using the same GND, particularly when it's a continuous plane, is sufficient for most designs. You shouldn't expect problems in JTAG configuration from this field of layout quality anyway. Leaving the enhanced pad unconnected however completely blocks device operation, including JTAG configuration.

0 Kudos
Altera_Forum
Honored Contributor II
1,092 Views

Thanks Frank 

I will work in the enhanced pad to be sure that it is connceted to GND.
0 Kudos
Altera_Forum
Honored Contributor II
1,093 Views

If the enhanced pad is correctly connected, it may be still a case of a damaged chip. As a another point, the Altera documentations always requests the MSEL pins to be pin strapped to a clear configuration scheme, whatever it is. Otherwise, also JTAG configuration can fail.

0 Kudos
Altera_Forum
Honored Contributor II
1,093 Views

Hi 

The MSEL pins (1,2 and 3) are connected to ground as indicated for JTAG configuration. 

Is there any special consideration to consider in the handle and mounting of the CycloneIII devices? (electrostatic discharge?) How can it be damaged? 

Thanks
0 Kudos
Altera_Forum
Honored Contributor II
1,092 Views

Your question can be answered very different. 

- There's always a certain risk of damaging electronic devices by ESD. Some reports say, that 50 % of unspecific device faults are caused by ESD events. It's recommended to use protection equipment not only in production but also in development and prototyping. 

- It's unlikely, that a particular device has been damaged by ESD in an usual lab enviroment. 

- More likely damaging mechanisms are overheating during solder and supply overvoltages 

- Potentially dangerous equipment are isolated SMPS without protective ground connection, either supplying a mobile computer or a development kit
0 Kudos
Reply