CONF_DONE pin failed to go high problem

[AlexHalf]

Hello

I am using EP4CGX150CF23C8N FPGA. Configuration is done in AS mode from EPCQ128ASI16N flash. All I/O banks are 3.3V. FPGA initial programming done through JTAG with Terasic USB blaster. Attached schematics with relevant connections.

My design is produced already - few hundred boards without any special issues.

Last week I started to design new Logic and Nios (in FPGA) versions and encountered phenomenon in 2 consecutive boards I tested.

In first board I programmed a jic file and it was working but suddenly it looks as it lost a configuration and board stacked (I am blinking few leds connected to FPGA and some of them also from Nios - and all leds just disappeared). Reburn with known released jic solved the issue. After burning of new jic again after few minutes of working - board stacked again. This phenomenon continued several times until it stacked without a recovery option. All tries to reburn the board with any image caused to failure of CONF_DONE. 

As I thought that I have an issue only with this single board I tried another new board.

Programming of this board with new jic succeeded and it worked. When I changed slightly again internal image and tried to burn with updated jic - it immediately failed on CONF_DONE error. And also as the first board from this failure it is impossible to reburn it with any jic - it always fail on CONF_DONE. 

As I have a remote update option I tried to burn the FPGA image (logic configuration + Nios firmware) on a third board through serial port to flash. It always success without any problems. These .flash files should have the same content as JTAG's jic file. This third board (where I not tried to burn jic file) is working.

In 2 failed boards I tried also to download only sof file (in order to eliminate effects of flash) - but without success (same CONF_DONE) error.

Voltages in both boards were correct.

Tried to reburn failed boards in another PC's (even with stand-alone programmer), another USB blaster and another power supply without success.

My questions:

1. Can it be that all this caused by jic files?

2. You think that maybe the issues I have are because of defected initial burning equipment like USB blaster or momentary problems in power supply that damaged 2 FPGA's? 

3. You think that I can ignore these phenomenon based on fact that I have few hundreds of working boards (even they burned only once from JTAG, while all updates if were needed were done from serial port with .flash files) or I must dig in my design in searching design issues?

Thank you 

[Fakhrul]

Hi AlexHalf,

My apologies, I missed your post. I'm trying to understand the situation here, appreciate if you could answer these:

1. does this issue only happen on these two boards? I understand you have tried on the 3rd board and working fine, correct?
2. Have you tried with a new jic generated from a new simple design?
3. Could you provide the error screenshot?

Regards,

Fakhrul

*Please be informed that we will be out of office from 8/April to 12/April due to a public holiday here. Kindly expect some delay in response if you are going to post an update.

[HAlex]

Hello Fakhrul

1. I tested with JTAG cable only 2 boards and with both of them have the same issue. Third board was burned in a different way - through remote update option (RS232 and not from JTAG).

2. I tried to burn 'damaged' boards with different validated jic files, also with simplified jic with empty project (just pins were defined) and even tried to download only sof file.

3. The screenshot of the message attached.

Thank you.

Alex

[Fakhrul]

Hi HAlex,

There's a KDB mentioning this kind of error, would you try to check this out? Sorry I may have overlooked your comment.

Why do I receive the error 'CONF_DONE pin failed to go high in device X' when I try to JTAG configure my Intel® FPGA using the Intel® Quartus® Prime Software and a download cable?

[Farabi]

Hello,

Do you have further question?

regards,

Farabi

[HAlex]

Hello

The NCE pin is do connected to GND as shown in the attached PDF of first message.

My questions as I posted:

1. Can it be that all this caused by jic files?

2. You think that maybe the issues I have are because of defected initial burning equipment like USB blaster or momentary problems in power supply that damaged 2 FPGA's? 

3. You think that I can ignore these phenomenon based on fact that I have few hundreds of working boards (even they burned only once from JTAG, while all updates if were needed were done from serial port with .flash files) or I must dig in my design in searching design issues?

Thank you

Alex

[Fakhrul]

Hi HAlex,

Based on current information, it is difficult for us to provide justification ie. this issue is due to jic file or not. However, may I know what is the version you're using now?

Are you performing any encryption in your programming?

There are a few KDBs may be related to your issue; some are not but it is worth the check it out:

Error (209014): CONF_DONE pin failed to go high in device 1

Error (209014): CONF_DONE pin failed to go high in device 1

Error (209014): CONF_DONE pin failed to go high in device 1.

Error (209014): CONF_DONE failed to go high in device <number>

Regards,

Fakhrul

[HAlex]

Hello

I am using Quartus Prime Version 21.1.0 Build 821 10/21/2021 SJ Standard Edition.

I don't have an encryption.

Tried to burn also with latest Quartus standalone programmer only with different verified jic and sof (only for FPGA download) files but without success.

Is it possible that FPGA is damaged (as sof file not working)? Or it still can be related to possible corrupted contents of flash that somehow overcomes even FPGA only sof file download attempts?

Thank you.

Alex

[Fakhrul]

Hi HAlex,

Could you try to connect the 0ohm resistor for nreset below?

Thanks,

Fakhrul

[HAlex]

Hello

Actually this 0-ohm resistor is do connected on the board even according to the flash datasheet it can be left unconnected.

Thank you.

Alex

[Fakhrul]

Hi HAlex,

Just want to confirm, If you directly program the FPGA through JTAG using sof file(not jic) , is it successful?

[HAlex]

Hello

No, sof file download is not successful.

It looks like the problem damaged somehow the FPGA and it is not reacting anymore to any FPGA download or flash burning attempt.

Thank you.

Alex

[Fakhrul]

Hi HAlex,

Can we have a short meeting via Teams?

The purpose of the meeting is to further understand more about the procedure that you are doing now.

I will send out the meeting invitation to your email.

Regards,

Fakhrul