Agilex7-I DEV kit CXL Example Memory Change Problem

[agilex7]

Hi

I'm creating cxl design using cxl example design supporting quartus 

Below is our test enviroment 

Test Enviroment

- Agilex DVE Kit : Agilex7-I DK-DEV-AGI027-RA

- Server : Intel CRB SPR CRB (CPU D0) 

- Quartus version : 24.3

- cxl design : cxl type3 membuffer example design 

First we've created cxl type3 example design (16GB memory) by Quartus

and we've seen cxl memory 16GB size in both uefi and linux also mlc test passed in the SPR CRB Server.

And next,  for memory capacity up, we've changed follow item.

- changed Componet dram to DIMM 16GB(Micron x4 RDIMM)  x2 (32GB) via EMIF ip  configuration 

- HDM capacity change  16GB --> 32GB ( hardware_test_design/ed_top_wrapper_typ3.sv  & intel_rtile_cxl_top_cxltyp3_ed/ intel_rtile_cxl_top_1120/sim/cxlip_top_pkg.sv mofied) refereced agilex7 cxl de ug ip document 

- In the cafu_csr0_wrapper.sv , we've chaged DOE enable to disable 

we've couldn't see cxl memory size in both uefi memmap and linux, but we've confirmed Memory Active(good), Media_type(00b) Memory Class(00b) via cxl devsec register in the Linux.

Dose anyone have any experience with this issue ?

[RongYuan · Accepted solution]

Hi,

Based on "Table 42. Updating HDM Size" in UG, you need to modify several files. Please make sure all these are updated.

Regards,

Rong

[agilex7]

Hi !

Thanks!

I will update all these files !~

[RongYuan]

If no further questions, I'll transit this case to community support. Thanks.

[agilex7]

I've solved this issue. I have no questions. Thanks!