Clarification on HBM Capacity and AXI4 Interface for Agilex 7 M Series

[admaris]

Dear Intel Technical Support, I have a question regarding the Agilex 7 M series FPGA, specifically related to the HBM (High Bandwidth Memory) configuration. 1、The maximum HBM capacity for the Agilex 7 M series is 32GB, but the NOC initiator AXI4 user interface has an address width of 44 bits. Given that 32GB should theoretically require only a 35-bit address width, I would like to understand why a 44-bit address width is used. Could you provide insight into the reasoning behind this? 2、Additionally, when reading and writing data in 512-bit chunks, is there any specific requirement regarding the user-side clock frequency? Specifically, is there a minimum or maximum frequency that the user-side clock must support, or can it be lowered to a specific frequency? Thank you for your assistance, and I look forward to your response. Best regards,

[sstrell]

The NoC can be used to access external memory (DDR4 or DDR5) as well as the on-package HBM2e so I would imagine the extra bits would be usable for that.

[Zehui]

Hello admaris,

Yes, the maximum HBM capacity is 32GB. However, those 32GB are split into two HBM stacks. There is only 16GB for each stack and we have to use two HBM IPs to fully utilize those 32GB.

https://www.intel.com/content/www/us/en/docs/programmable/773264/24-3/m-series-hbm2e-introduction.htmlhttps://www.intel.com/content/www/us/en/docs/programmable/773264/24-3/axi4-interface-signals.html

A single NoC Initiator can talk to multiple NoC targets (HBM, DDR4, DDR5, LPDDR5). Those extra bits are used to select different targets.

Regarding clock frequency, please have a look at this document. It shows all clocking schemes of NoC.

https://www.intel.com/content/www/us/en/docs/programmable/788295/23-3/planning-noc-and-memory-solution-clocks.html

Thanks.