CONF_DONE pin not going high when trying to program Cyclone III with an SOF file

[Altera_Forum]

I have a problem very much similar to a thread posted some time back but the solution mentioned for that ie connecting nCE pin to ground is not working in my case. Actually nCE is already connected to ground for my card. I have designed a card with Cyclone III programming being done through JTAG as well as through AS configuration scheme. The configuration of all( around 10 cards )but one card is going very well, using either SOF or .JIC. I actually have three devices connected in JTAG chain. initially when i am trying to program the FPGA while all devices in chain, the quartus does not give any error while programming with SOF or JIC. but the FPGA was not coming up, that is its not getting programmed which is indicated by some leds still off. i removed other devices from the chain and tried again. this time the Quartus s/w gave an error that CONF_Done pin not going high while no error when loading with .JIC file. for all, FPGA still not up. i have checked all connections, resistors, pull ups and pull downs. everything is fine as in rest of the cards.I HAVE ABSOLUTELY NO IDEA WHATS WRONG. Can ne one give a clue?

[Altera_Forum]

Hi, 

 try this link  http://www.altera.com/support/kdb/solutions/rd07202009_82.html  Thanks

[Altera_Forum]

This link tells about the PLC option under convert programming files means i need to convert sof file to some other programming file before loading that image in FPGA.I tried generating a .jic file but the problem is how will the s/w tell whether it is early or late CONF_DONE assertion as the flash will load the image once we reboot the card..during which the quartus is not related to whats happening between the FPGA and the flash. or what other programming files can be generated for this debugging. I tried pof also.that dint help.

[Altera_Forum]

Finally the card came up..dont know why it shud have not programmed . except CONF_DONE , both nStatus and INIT_DONE were high when i measured using a multimeter. I tried probing CONF_DONE to see whether it goes high any time before/during/after configuration.It was low always.and the FPGA still dint get configured, though i got the error now even when all devices were in chain. again i dont know why this change happened. Next, i switched to probing nStatus and voila!!! it configured..!!:D I guess it provided some capacitance. I will be grateful if any one can explain this to me. 

I was also unable to program the serial flash in the same powered state. i took out the card and re inserted it and it worked.   no changes , no settings it needed. Sometimes electronics is so weird!!

[Altera_Forum]

You need to reboot after programing a .jic file. 

You can not reboot after programing with a .sof file (the internal SRAM gets cleared). Conf_done only works if activated in the device configuration settings.

[Altera_Forum]

--- Quote Start ---  Finally the card came up..dont know why it shud have not programmed . except CONF_DONE , both nStatus and INIT_DONE were high when i measured using a multimeter. I tried probing CONF_DONE to see whether it goes high any time before/during/after configuration.It was low always.and the FPGA still dint get configured, though i got the error now even when all devices were in chain. again i dont know why this change happened. Next, i switched to probing nStatus and voila!!! it configured..!!:D I guess it provided some capacitance. I will be grateful if any one can explain this to me. I was also unable to program the serial flash in the same powered state. i took out the card and re inserted it and it worked.   no changes , no settings it needed. Sometimes electronics is so weird!!  --- Quote End ---    hi there im having the exact same problem as you (getting no error while programming, fpga will not come up), trying to program with signaltap also gives no errors though it still prompts me to program my device (again and again after programming..), i also have checked the connections, checked to see that i am getting data&clock during programing, and still fpga wont come up. tryed to program several sof's that surely worked in the past, getting nothing.. could you think of anything else that you've done besides probing the nStatues that fixed things up for you? thanks

[Altera_Forum]

I dont remember if i had anything else other than probing at various points. Try providing a capacitor between DCLK and gnd.  

"trying to program with signaltap also gives no errors though it still prompts me to program my device (again and again after programming..)" Do you mean that you are not able to program through sof file also? Check for any reset that you may have provided to fpga . you can also connect an LED to any fpga pin and drive that to see if fpga is configured anytime.

[Altera_Forum]

--- Quote Start ---   "trying to program with signaltap also gives no errors though it still prompts me to program my device (again and again after programming..)" Do you mean that you are not able to program through sof file also?  --- Quote End ---   thats the thing, i can see the programming sequence completes, quartus's console prompts "ended programming succesfully" and signaltap has a red mark telling me to program the device again, trying to start the sampling with/without a trigger option chosen changes the red mark to a yellow mark saying "jtag communication error", how can there be an error when it is beeing recognized by the programmer while pressing "find target" or using the jtag debugger successfully?     --- Quote Start ---   I dont remember if i had anything else other than probing at various points. Try providing a capacitor between DCLK and gnd.   --- Quote End ---   i see, i appriciate the effort, everything in my design is connected based on the cyc III datasheet so if it asks for a capacitor im pretty sure it has one, though i will go and check as soon as i can    --- Quote Start ---   Check for any reset that you may have provided to fpga . you can also connect an LED to any fpga pin and drive that to see if fpga is configured anytime  --- Quote End ---   another thing id like to add is that my design did function on previous versions, trying to program 100% previously working back up sof's failed as well but it did used to work for several months before this problem occured