I wish to use configuration error detection IP to report corruption of the configuration image but I am not sure what I/O standards are available on the CRC_ERROR pin.
The 'device and pin options' of Quartus has a tick-box called "Enable open drain on CRC_ERROR pin". If this is not ticked, what output drive circuit can I expect? Will it actively drive the pin to VCCIO when an error occurs and pull it to GND when there is no error? And which I/O standard will this be? Also, what is the behaviour of the pin during configuration and during initialisation?
The handbook also talks about a "cycloneiv_crcblock" primitive atom. Does anyone know what a primitive atom is and how I can use it to access the CRC storage register to inject an error?
The device is Cyclone IV E. Quartus prime 18.0.
For voltage level check the voh voltage based on I/O Standard or VCCIO of bank 6.
CRC error detection is only supported in Cyclone IV E devices with VCCINT 1.2 V, and not in Cyclone IV E devices with VCCINT 1.0 V.
Hi, thanks for your great answer.
Perhaps intel can clarify the use of that tick-box because I found a knowledge base entry (link below) which agrees with your answer and states that the box is greyed-out from Quartus10 onwards. Fair enough it, has had many versions since and they may have a reason to start using the box again but the fact it isn't greyed-out any more suggests to users that it has a function again.