CRC calculation time for Cyclone 10CL040YU484I7G

[MFerr15]

Hi,

I was reading the Cyclone 10 handbook and in section 7.3.1.5 are presented CRC calculation times for the minimum and maximum frequencies.

I have three question: what does this value means and what are the values for frequencies other than the maximum (80 MHz) and minimum (312.5 kHz).

Does the FPGA speed grade plays a part in this calculation or is it the same for all grades.

Cheers

[Rahul_S_Intel1]

Hi , This is the feature provided in the Cyclone 10 LP.There is a hard block (circuitry ) for the error detection cyclic redundancy check (CRC). To enable you can use 7.4 section of the below document. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.pdf Regards, Rs

[MFerr15]

Hi, thank for your reply. As I mentioned in my post above I read the handbook, but there isn't any mention to a formula to calculate these times. In other handbook (e.g. Cyclone V) there are formulas describing the maximum and minimum times for the different frequency dividers (in page 288 of the Cyclone V handbook 1). Should I assume the formula is the same? If not how do I calculate.

I also don't find any answers to my other questions in the handbook, namely the speed grades of the devices..

Cheers

[Rahul_S_Intel1]

Hi , I understand, but for the Cyclone 10 LP, the only information for the CRC time calculation available is section 7.1.1.5 Table 56 . And the there is not given any formulat for the time taken, only formulat is error detection frequency page no:165 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.pdf