I was reading the Cyclone 10 handbook and in section 184.108.40.206 are presented CRC calculation times for the minimum and maximum frequencies.
I have three question: what does this value means and what are the values for frequencies other than the maximum (80 MHz) and minimum (312.5 kHz).
Does the FPGA speed grade plays a part in this calculation or is it the same for all grades.
Hi, thank for your reply. As I mentioned in my post above I read the handbook, but there isn't any mention to a formula to calculate these times. In other handbook (e.g. Cyclone V) there are formulas describing the maximum and minimum times for the different frequency dividers (in page 288 of the Cyclone V handbook 1). Should I assume the formula is the same? If not how do I calculate.
I also don't find any answers to my other questions in the handbook, namely the speed grades of the devices..