CVO underflows - DDR2 HPC perfomance problem?

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CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

CVO underflows - DDR2 HPC perfomance problem?

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Hi,

I have to show 3 PiPs on 1280x720 50p output. The incoming videos are siimple 720x576 PAL video, resized, cropped, de-interlaced, whatever-ed to 640x360. Up to 2 the system just works fine, I can move, resize, etc the PiPs, but as I add the 3rd video input AND switch on ANY incoming layer form the three, the CVO underflows and locks. I have to reset the system.

It seems I have DDR2 HPC2 performance problem. But 3x video ST does have very small load on bandwidth. No other IP uses the RAM (de-interlacer, or resize, etc.)

A simple block diagram is attached. Any advice is very much welcome!

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