Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21600 Discussions

Calculating the number of gates I need..??

Altera_Forum
Honored Contributor II
1,720 Views

I wonder how I can calculate the number of gates I will need for an application. 

For example, if I need a 16Bit-Counter, how much gates will this need? 

Which device will fit this application?
0 Kudos
6 Replies
Altera_Forum
Honored Contributor II
813 Views

First guess: A 16-Bit counter occupies 16 logic elements. The smallest family member of the Cyclone III family features about 5000 LE. Such simple application will fit into every device Altera ever have produced. 

I would suggest to try out. Write some HDL code and let Quartus tell about the ressource usage.
0 Kudos
Altera_Forum
Honored Contributor II
813 Views

OK, that means, you first design your application with Quartus and it will tell you what device you need. After this you will design your board with the suggested device.  

 

But what, if you had to design both in parallel ? 

Daniel
0 Kudos
Altera_Forum
Honored Contributor II
813 Views

Seems you actually mean how to estimate the resource needed for a given design. So far this is an issue of informed guess and some research. 

It is interesting that this issue is never addressed by any tool makers, I guess it is quite difficult and is related to another issue: how good is the design work? 

For a given functionality, some designers or tools produce tons of code and spaghetti logic while others go for better method. 

I believe in this principle: There is always a better way of design, find out... For example if you need 100 counters each 14 bits you will need 1400 registers plus 100 adders ...etc. This will consume a large area of chip. But you can use an alternative, implement counters in memory blocks, find out?? 

 

Don't forget resource sharing if you can go fast.
0 Kudos
Altera_Forum
Honored Contributor II
813 Views

If you have to do FPGA design and board design in parallel then you have to estimate the ressource usage. This should be done by experienced FPGA designers. There is a possibility to do that board layout for two different devices and decide later which one to use. Altera calls this migration device. But to be honest, I never had to use this. 

Do you use IP cores? A DRAM controller? A NIOS? In that case you can find information about the ressource usage of these modules. For the rest you will have to estimate.
0 Kudos
Altera_Forum
Honored Contributor II
813 Views

True as Harald says about Migration.  

But you may decide your pins early and may not need any extra pins later but just extra internal resource. 

For this end some devices are manufactured as a set of different sizes but with same footprint, the largest device will have the full set of pins, smaller devices will be subset of the main pinout. Then you can start buying largest device of a set and then migrate down if necessary provided you have used the correct subset of pins on your board.
0 Kudos
Altera_Forum
Honored Contributor II
813 Views

DanVet 

 

If you want a rule of thumb for guessing then here's mine: 

 

Sketch out your design very roughly and do a rough calculation based on what you think will be in it: 

 

e.g. 16 bit counter - 16 LEs 

32 bit shift register - 32 LEs 

 

Add say 30% because of all the bits you missed - all the little lumps of logic that glue all these bits together that you didn't think of at the time but suddenly appear along the way and mount up. (Also requirements will almost certainly change and you'll have to add a few bits because it doesn't quite work how you thought it would). 

 

Add all of this together and aim to come in under 80% of the chip. Use this as a risk management guess only - don't make any assumptions on it. 

 

I would say this works reasonably well for designs where area is more important than speed - e.g. if speed is a serious requirement then aim to use up less than 80% of the chip. 

 

Other people may well reply and say this is a load of dingo's kidneys and they will be perfectly right in doing so - it is only a rule of thumb that I have used in the past to get a very rough idea of logic requirements - don't spend money based on this! 

 

Basically this is a risk and you need to manage it as so: 

 

1) Regularly synthesise / place and route your design as it develops so you get an early a warning as possible if you're starting to get a bit big. 

 

2) Early on in the project, make sure you identify space and device choice as a project risk to the project manager - don't keep it to yourself and hope it works out. 

 

As somebody else said, the best tool in estimating design size is experience and even with experience I would say it's still a bit of a stab in the dark. 

 

Hope this helps.
0 Kudos
Reply