Can Cyclone IV JTAG VCC use separate 2.5V instead of VCCA?

[Altera_Forum]

The Cyclone IV handbook in section 8-47 says: 

   --- Quote Start ---    For device using VCCIO of 2.5, 3.0, and 3.3 V, refer to Figure 8–23. All I/O inputs must maintain a maximum AC voltage of 4.1 V because JTAG pins do not have the internal PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and 3.3 V. You must power up the VCC of the download cable with a 2.5-V supply from VCCA.   --- Quote End ---     However, as the current layout stands it is inconvenient to send the VCCA plane to the jtag connector. It is far more convenient to have a small local 2.5V linear regulator instead (I have a nice little spot for it). I understand that the reason for the 2.5V instead of VCCIO (which is 3.3V in this case) it to get farther away from the 4.1V overshoot (not sure why not just install the clamping diodes to VCCIO instead of using the VCCA PLL supply). But what bothers me are the words "MUST" and "FROM" in:     --- Quote Start ---  You MUST power up the VCC of the download cable with a 2.5-V supply FROM VCCA.  --- Quote End ---    I don't think there would be any problem in supplying the 2.5V from a different regulator than VCCA, but I'm asking here just in case anybody knows. The only thing that occurs to me is timing (driving JTAG before VCCA is there), but those pins are supposed to be powered by VCCIO, so I don't see how that could be the case.

[Altera_Forum]

--- Quote Start ---  However, as the current layout stands it is inconvenient to send the VCCA plane to the jtag connector. It is far more convenient to have a small local 2.5V linear regulator instead (I have a nice little spot for it). I understand that the reason for the 2.5V instead of VCCIO (which is 3.3V in this case) it to get farther away from the 4.1V overshoot (not sure why not just install the clamping diodes to VCCIO instead of using the VCCA PLL supply).   --- Quote End ---    I completely agree with your analysis. You MUST observe the FPGA maximum ratings. If you achieve it e.g. by JTAG clamp diodes, it's O.K. as well. Up to now, I'm using 3.3V JTAG for all Cyclone I to IV devices, with respective protection means.

[Altera_Forum]

I don't use any protection on JTAG and had no problems. Look to the possible problem from the other side: what can cause voltage overshot in the USB Blaster if it's properly made by Altera?

[Altera_Forum]

--- Quote Start ---  what can cause voltage overshot in the USB Blaster if it's properly made by Altera?  --- Quote End ---   Good question. In fact, a PCB trace of some length or an IDC cable can be sufficient, due to the low driver impedance of some USB Blaster versions.   The below documented waveform has been acquired with an Altera Cyclone II evaluation board near the FPGA, using a Rev. B USB Blaster.

[Altera_Forum]

So there are no serial resistors in USB blaster?

[Altera_Forum]

The said Rev. B USB Blaster had been equipped with a rather low series resistor (10 ohm or so). And shipped with a special flex print cable with low characteristic impedance. This moved the impedance matching problem to the JTAG connector, but didn't solve it. And the flex cable was often replaced by a regular IDC cable, because the original cable broke easily and was too short or to rigid in many cases. 

 Newer USB Blasters and the present Terasic model have less overshoot as far as I'm aware of.

[Altera_Forum]

@FvM, in another thread (.../showthread.php?t=1779# 4) you mentioned a relationship between using 2.5V for configuration and an issue with power up sequence. Could you expound or cite a source?

[Altera_Forum]

I'm referring to respective comments in the Cyclone III device handbook. I don't expect any problems as long as the supply rails power up regularly. I have mostly a switcher powered 3.3 V rail and 2.5 V VCCA and LVDS VCCIO generated by a small LDO. So you can expect both starting simultaneously. None of the fault scenarious discussed in the device handbook can take place here.