- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I have a question about DDR usage:
1. Can HPS arm and FPGA fabric share DDR.
2. if DDR has 4 channels, can HPS use 2 channels to access DDR and FPGA fabric access through the other 2 channels? but they are independent access?
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi lidongyang
Yes you are able to share DDR between the FPGA Fabric and HPS arm.
HPS Arm is able to access the DDR through the DDR Controller or HPS EMIF depending on device through the L2 Cache. The FPGA Fabirc is able to access the DDR through the FPGA2HPS bridge through the L3 cache.
Which device you are using at the moment?
Regards
Jingyang, Teh
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Jingyang,
Many thanks for your reply. The FPGA we use Agilex 7 FPGA.
"HPS Arm is able to access the DDR through the DDR Controller or HPS EMIF depending on device through the L2 Cache. The FPGA Fabirc is able to access the DDR through the FPGA2HPS bridge through the L3 cache."
the following questions:
1. If ARM put the OS region such as boot code and OS running region to offset 0x000-0x100 for example. How to ensure the FPGA fabric cannot touch that area?
2. is there any example project I can reference for the HPS connection. (ARM+FPGA access same ddr region)
Thanks again.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi lidongyang
The assigning of variable will be done by the OS. The assignment of the variable will be set by the OS. It will be assigned on the execution of the application.
You could refer to this example design
FPGA-to-HPS Bridges Design Example | Intel
Regards
Jingyang, Teh
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi lidongyang
Any new updates on this case?
Have you take a look at the example design?
There are two methods of read using the DMA (Cacheable and non-cacheable)
Regards
Jingyang, Teh
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Jingyang,
So many thanks for the follow up.
I have not yet work on the example because of my task changes. Please close this case for now.
I will try it out as soon as possible. and reopen the case.
Thanks.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi
Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome to reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 4 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.
Regards
JIngyang, Teh
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page