Rise Time / Clock buffer impact on Stratix 2

[_DMW_]

Hello, 

I'm looking to change an oscillator that inputs into a stratix2 fpga. 

One of the constraints is not changing the firmware.

The clock signal gets fed directly into on of the global clock buffers and spread round the chip.

Does the global clock buffer change the signal in any way? Would it improve the edge?

If not, what part of the timing budget would an increased rise time eat into?

Thank you

[TingJiangT_Intel]

The significance of a global clock lies primarily in its dedicated routing resources, especially for clock signals with large fan-out. Routing these signals through the global clock ensures that, during the layout and routing process, the wire lengths for the clock signals reaching various registers are approximately equal. This, to a certain extent, helps reduce the differences in clock skew.

[_DMW_]

Thank you for your response.

I'm more interested on the impact of the literal rise time of a single clock, as opposed to it's skew vs other clocks. 

Is there any documentation that discusses the rise time of signals?

And/or what portion of the timing budget it might eat into?

Apologies if this is basic, my background is hardware and I'm relatively new to firmware.

[TingJiangT_Intel]

In fact, we barely pay attention to the rising time when designing,The signal recognition inside the device is also based on the level. As long as the level reaches Vh, the signal is considered to have reached a high level, and generally not too much attention is paid to the time it takes to rise.