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Altera_Forum
Honored Contributor I
933 Views

Can HPS verify FPGA configuration?

I have a Terasic DE-10 kit, and some of the sample programs require me to program the FPGA externally through JTAG and then run a program on the HPS which utilizes this configuration. Is there any way for the HPS to verify the configuration of the FPGA? For instance, if I flash the wrong configuration, can the HPS double check this (with a hash value or something) before running it's code?  

 

Similarly, is there a way for the JTAG programmer to confirm that the configuration was successfully written to the FPGA? The Quartus programmer shows that the operation is successful, but is the programmer actually aware of errors that might have occurred on the FPGA side? E.g. is it possible for the FPGA to check the validity of the configuration and respond back to the programmer? 

 

I understand that it is impossible to read back the full configuration of the FPGA, so I was wondering if there is any formal way to validate the FPGA configuration for the sake of security. 

 

Thank you.
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2 Replies
Altera_Forum
Honored Contributor I
38 Views

You can achieve to a certain extent some verification. 

 

Firstly the HPS can verify whether or not the FPGA is configured via control signals in the HPS bridge. The preloaders frequently use this to determine the state of the FPGA during boot. 

 

I don't believe there is a way for the HPS to directly determine if the correct file was configured - it can determine it was correctly configured, but not what file was used. In some ways it is possible to assist in checking by adding to each design a system ID block which is unique to the design (including timestamp so version can be checked). The preloader can then check the system id and timestamp through the HPS bridge. If it finds the right values, it knows the right design is loaded. 

 

In terms of JTAG programming, the Quartus programmer will only show successful operation if the operation is successful. CRC verification is performed on each block of the image file, and it can verify that the contents of the SRAM in the FPGA matches what it uploaded (the "Verification" step). In fact the JTAG programmer can also "read back the full configuration of the FPGA" quite happily - the "Examine" step. I don't believe the HPS can though. 

 

Another option you have is to store the FPGA image on the boot media with the HPS software. The FPGA can be programmed by the HPS - so if the HPS has the image it wants to upload to the FPGA, it can check the image is correct before uploading it. Once it finds the image file is correct, it will upload it and because of CRC checks the FPGA will be able to tell it that configuration was successful (indicating the file was programmed correctly).
Altera_Forum
Honored Contributor I
38 Views

If you are wiling to invest in Design Security, you can choose to blow the fuses in the FPGA - in this way only the FPGA Image compiled and encrypted with the same fuse key can be programmed to the FPGA. Note however that this verification of the keys happen in the FPGA and the HPS has no idea if the key is mismatched (it will report configuration failure)