Can I use CLK_n pin for user logic in case I'm using CLK_p as single ended CLK pin?

[IDeyn]

Hi all!

The question is - FPGA device (for example Cyclone V) has several CLK_p and CLK_n dedicated clock pins. If I choose CLK_p for being the input of clock because of dedicated routing to PLL input, how could I use CLK_n? Could I use it without any concern as GPIO for logic or better for example not to do it and tie it to GND?

Thanks a lot.

Ivan.

[a_x_h_75 · Accepted solution]

Yes - for Cyclone V anyway. It may not be the case for all, particularly older device families. Refer to the pinout file for a specific device. It will list the 'Pin Name/Function' and an 'Optional Function' - where you will find reference to the clk_p. Providing you have 'IO' in the Pin function column it'll work as a general purpose IO pin.

Cheers,

Alex

[IDeyn]

Thank you very much for your answer, a_x_h_75!

I was almost sure that I could use CLK_n as GPIO, but wanted to be confident. Because of dedicated nature I thought that maybe CLK_n is constrained of its SSN impact or maybe those pins have higher capacity...