Can Stratix V IO pin configure with HSTL12 class 1 work at 0.8V

[jkhoo]

Hi PSG team,

My i am currently sourcing 0.8V into VCCIO for very bank in stratix V and it is working.

Based on DC and Switching Characteristics for statix V devices, HSTL-12 Class 1 VCCIO is paper spec at min 1.14V, typ 1.2V, max 1.26V.

Since by sourcing 0.8V to VCCIO, stratix V output is now transferring data to downstream device, where the data toggle from 0V to 0.8V. and is able to meet the downstream device VIH min/max. 

What is the risk of operating below the min 1.14V pec?

[FvM]

Hi,

reading device datasheet strictly, operation isn't guaranteed for nominal VCCIO below 1.2  V (1.14 min.).

In so far seeing the device operating correctly in your test proves nothing, particularly not operation over full temperature range or for devices with marginal parameters.

Regarding risk, at least I won't expect damage with VCCIO below specified range.

[jkhoo]

Hi FvM,

Many thanks for responding, your statement on PVT (Process, Voltage, Temperature) range does make sense. when i am testing and it is passing, i am only testing in a sub range of the full PVT range.

But, I am of the impression that HSTL-12 Class I is a type of digital logic signaling standard and only specifies how signals at the IO pins should be driven, terminated, and received to ensure reliable high-speed data transmission. It is not a specific circuit design. So, in the case of output buffer of the bank, am I correct to say that HSTL-12 Class I spec is just spelling out the voltage swing condition of the data that is transmitted to the downstream DUT/device. As long as the downstream DUT/device is also HSTL-12 class-I compliance, its Vil/Vih will be able to interpret a logic 0 and logic 1.

Having said that, does it also means that when i source VCCIO rail with 0.8V, the FPGA output buffer will swing between 0V to 0.8V and as long as the downstream DUT/device Vil/Vih is capable of interpretating a logic 0 and logic 1 with a acceptable margin, the operating condition is still predictable.

[FvM]

Hi,
I wasn't talking particularly about HSTL-12 IO standard. The simple fact is that neither Stratix V nor other recent Intel FPGA support any IO standard below VCCIO 1.2 V. This suggests that no device is tested is with e.g. 0.8 V.

[jkhoo]

Hi Fvm,

Noted on your point.

Regards, JJ

[jkhoo]

Extra question,

If i am force by situation to source 0.8V into VCCIO while configuring the IO buffer/pins to HSTL-12 Class 1 standard, which particular electrical parameter that may shift?

1. will the Vth change resulting in worst duty cycle distortion?
2. will the IO buffer well biasing become more stressful resulting in reliability issue?
3. what will the voltage difference between VCCPD(at 2.5V) vs VCCIO(at 0.8V) cause?

[AqidAyman_Intel]

Hi JJ,

From what I understand, if it is not fulfill the requirement in the datasheet, we can't predict the outcome or absolute effect to the device's electrical behavior. It is not guaranteed the operation if it is out of specs.

Regards,

Aqid

[AqidAyman_Intel]

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