Can't ECO modify PLL's properties of Cyclone V devices?

[Altera_Forum]

Hi guys, 

  I want to make some small modification on PLL of Cyclone V devices. However, it seems i can't do anything thru ECO on it as altera previous generation deivces (for example Cyclone III). Why?

[Altera_Forum]

The PLLs on the Cyclone V don't work the same as the earlier parts. Read the PLL chapter of the device handbook. Since you didn't give any details on what you were trying, I can't say why it doesn't work.

[Altera_Forum]

--- Quote Start ---  The PLLs on the Cyclone V don't work the same as the earlier parts. Read the PLL chapter of the device handbook. Since you didn't give any details on what you were trying, I can't say why it doesn't work.  --- Quote End ---    I want to modify the PLL's output's phase after full compilation, so i used to use ECO to modify it. Which makes me implemented it fast whitout full complie my project again.

[Altera_Forum]

Hello, have you tried to follow http://electro-logic.blogspot.it/2015/09/fpga-engineering-change-orders.html (hello, have you tried to follow http://electro-logic.blogspot.it/2015/09/fpga-engineering-change-orders.html) ? 

I think it is done with Cyclone IV but should works also with Cyclone V. Are you using Cyclone V PLL IP?  Tutorial is in Italian but you can translate it with Google or Bing.

[Altera_Forum]

Altera app note 661 "Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores" seems to explain how to do this. Examples 2 and 4 are on phase shift. This is different from Cyclone IV.

[Altera_Forum]

--- Quote Start ---  Hello, have you tried to follow http://electro-logic.blogspot.it/2015/09/fpga-engineering-change-orders.html (hello, have you tried to follow http://electro-logic.blogspot.it/2015/09/fpga-engineering-change-orders.html) ? I think it is done with Cyclone IV but should works also with Cyclone V. Are you using Cyclone V PLL IP?  Tutorial is in Italian but you can translate it with Google or Bing.  --- Quote End ---    Hi Flz,  I'm using CV PLL. I can't open your link.

[Altera_Forum]

Here is the link: 

 http://electro-logic.blogspot.it/2015/09/fpga-engineering-change-orders.html (http://electro-logic.blogspot.it/2015/09/fpga-engineering-change-orders.html)

[Altera_Forum]

Yeah, with Cyclone V you have to use Altera PLL Reconfig IP

[Altera_Forum]

--- Quote Start ---  Yeah, with Cyclone V you have to use Altera PLL Reconfig IP  --- Quote End ---    Hi flz  I don't want to use pll reconfig, i just want to modify the PLL manually after full compilation!

[Altera_Forum]

As far as I can tell, flz47655 is correct. The only way to changes the phase of a clock after compilation on Cyclone V is to implement PLL reconfiguration with the Altera IP.

[Altera_Forum]

--- Quote Start ---  As far as I can tell, flz47655 is correct. The only way to changes the phase of a clock after compilation on Cyclone V is to implement PLL reconfiguration with the Altera IP.  --- Quote End ---    Hi Galfonz,  Is it means altera doesn't open ECO for PLL to users? Does ALTERA plan to open it to users?

[Altera_Forum]

No way to make ECO on PLL due to different structure..

[Altera_Forum]

This is a Cyclone V hardware issue, not something that could be changed with a Quartus update. As far as I know the reconfiguration scheme is the only way to adjust clock phase. It can't be done dynamically like the Cyclone IV and before. Re-configuring and waiting for it to lock again is the only way I know of.