Can't achieve minimum setp and hold time error?? :((

[Altera_Forum]

The scenario is that I have a (1) grey code counter connected to a (2)combinational block that goes into a (3)parallel In parallel out register from there.  

There are 2 inputs from the Grey counter and four other inputs that go into the combinational block that makes 6 inputs. The combinational block has 4 outputs 2 of these depend on the Grey counter (which is synchronus) the other 2 don't.  The problem. The Memory Block which is (3) as defined above is enabled for only 1 clock cycle to store what is coming into it from (2).  Now the problem  Warning: Can't achieve minimum setup and hold requirement Clk along 3 path(s). See Report window for details.  Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.   Now what the report says is as follows: The timing analyzer summary   Clock Hold: 'Clk'   -2.000 ns   1.00 MHz ( period = 1000.000 ns )  N/A   RowScanner:inst|rScan_GrCounter:inst|D0   keyStoreMem:inst2|FF3   Clk   Clk   3  Where RowScanner is the block that contains (1). The keyStoreMem is (3). Also the Clock Hold: 'Clk' says that:  -2.000 ns RowScanner:inst|rScan_GrCounter:inst|D0 keyStoreMem:inst2|FF3 Clk Clk 0.000 ns 6.000 ns 4.000 ns  -2.000 ns RowScanner:inst|rScan_GrCounter:inst|D1 keyStoreMem:inst2|FF3 Clk Clk 0.000 ns 6.000 ns 4.000 ns  -2.000 ns RowScanner:inst|rScan_GrCounter:inst|D0 keyStoreMem:inst2|FF4 Clk Clk 0.000 ns 6.000 ns 4.000 ns  why is this happening with my design? I have also tried to invert the clock going into the memory so that instead of the positive edge it shall update on the negative one but still no use. Please don't be scared by this complicated message. Any help is appreciated.:)

[Altera_Forum]

Right-click on one of the failing paths and do a List Paths. You'll see detailed information you break out on the path below. 99% of the time when there's an internal hold violation, it's because you have a gated clock(i.e. there is logic on the clock path going to the memory.) If this is the case, you want to remove that so the clock directly feeds all logic, and use synchronous logic to control when the memory is written to.

[Altera_Forum]

see I have a block with Parallel in parallel Out D flip flops. The CLK to them has been inverted by using a NOT gate and Also I have use a D flip flop to create a Clock enable thing instead of an AND gate having a clock enable and CLK signal input.  

 Then I have a Grey Counter that still has the AND gate with the Clock enable and CLK inputs. I replaced that with a D flip flop with the Clock enable going into D and the CLK going into its clock input in order to replace the AND gate but then nothing works. What should I do. This is the first time I am working on Quartu. Is there any advice that you may give me then?

[Altera_Forum]

It's a hold violation, so I would say almost with certainty you have a gated clock to keyStoreMem:inst2|FF*. You can do the List Paths to determine this too. Describing the circuit doesn't help much. 

The only thing that's "strange" is that all your slacks are the same. In generally they're going to vary to each destination(even if they're all failing), but I'm not sure why. Anyway, have you done the List Paths? What have you found from this?