Re: Can't fit design in Cyclone V GX

Altera_Forum · ‎06-01-2017

Hi everyone,

I'm trying to complete the My First FPGA tutorial (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/tt/tt_my_first_fpga.pdf) and everything works perfectly up until compilation, at which point it gives me error 11802 ("Can't fit design in device"). This is confusing as the flow summary doesn't say that a significant amount of anything is getting used.

I saw that this was an error with Quartus II but I'm using Quartus Prime Lite so I can't find anything else on it.

Any help would be greatly appreciated :)

Altera_Forum · ‎06-01-2017

Quartus prime is a newname for Quartus II (as far as I know) So what you saw might help you as well

Altera_Forum · ‎06-01-2017

--- Quote Start ---

Quartus prime is a newname for Quartus II (as far as I know) So what you saw might help you as well

--- Quote End ---

I'll try what the page suggested - thanks!

Altera_Forum · ‎06-01-2017

--- Quote Start ---

Quartus prime is a newname for Quartus II (as far as I know) So what you saw might help you as well

--- Quote End ---

So I just tried the fixes that were suggested, and none of them worked. It's especially odd since my design appears not to be taking up a significant amount of space. Here's what I get from the top.fit.summary file:

Fitter Status : Failed - Thu Jun 01 17:15:25 2017
Quartus Prime Version : 17.0.0 Build 595 04/25/2017 SJ Lite Edition
Revision Name : proj2_top
Top-level Entity Name : proj2_top
Family : Cyclone V
Device : 5CGXFC7D6F27C7
Timing Models : Final
Logic utilization (in ALMs) : 24 / 56,480 ( < 1 % )
Total registers : 32
Total pins : 6 / 378 ( 2 % )
Total virtual pins : 0
Total block memory bits : 0 / 7,024,640 ( 0 % )
Total RAM Blocks : 0 / 686 ( 0 % )
Total DSP Blocks : 0 / 156 ( 0 % )
Total HSSI RX PCSs : 0 / 9 ( 0 % )
Total HSSI PMA RX Deserializers : 0 / 9 ( 0 % )
Total HSSI TX PCSs : 0 / 9 ( 0 % )
Total HSSI PMA TX Serializers : 0 / 9 ( 0 % )
Total PLLs : 1 / 16 ( 6 % )
Total DLLs : 0 / 4 ( 0 % )

As you can see none of the resources are even close to over 100% used. :/

Altera_Forum · ‎06-01-2017

Update -- there was something wrong with the .sdc file I created from the tutorial -- removing it made the compilation work. I'll look into that issue further.

Altera_Forum · ‎06-21-2017

The Quartus fitter also says sometimes "can't fit design in device" when there is something wrong with pin assignments... so that error message can be confusing. Look in the report if you have other errors or warnings just before the "can't fit in device" error.