Can unused VREFB pins be FLOATED in Cyclone10 LP ?

[xytech]

Hi there,

We use 10CL055YU484C8G.

In Intel's 《cyclone_10_lp_schematic_review_worksheet.doc》and 《Pin connection Guide.pdf》, it requires "If VREF pins are not used, designers should connect them to either the VCCIO in the bank in which the pin resides or GND. Ensure the reserve unused pin option used in Quartus Prime software for these pins do not conflict with the board connection"

Question: If we do not use VREFB pins, can they be FLOATED (Not connect to anything)? Why need to connect to GND or VCC_IO, which may cause damge if Quartus setting are errorous...

Thanks!

[xytech]

up

[SreekumarR_G_Intel · Accepted solution]

Hello , Thank you for the question , To answer your question why , Can you kindly look at the diagram Figure 65 or 66 ? Those IO standards are voltage reference IO std.Keeping the VREF pin as floating what is the output of the buffer logic which is undefined right ? Assume now you connected to valid logic 1 or 0 , then based on the input it is predictable answer. That mean, you no need to care about what voltage you think it should be high /low since it is unused for your logic , but atleast that pin should be valid logic as HW should work as expected. Suppose in your design if you left open the VREF pin , you can configure as IO and enable the weak pull up. Hope helps . Thank you, Regards, Sree

[xytech]

Hi Sree, understood. That's very kind of you. Thanks!​

[xytech]

Hi Sree,

Another related question is, suppose some designer made mistakes that "Reserved unused pin option setting in Quartus Conflict with the real board connection", for example, Quartus sets the unused pins as "output driving GND", wihle the real hardware connets them directly to VCCIO.

What would happen? Will the IC be damged, or it will automatically omit the wrong settings in Quartus , and run with the real hardware connection? Just want to know how will Intel FPGA handle this kind of conflicting situation.

​Thanks!

[Abe]

This could potentially damage the FPGA pin/IO as the IOB is driving the pins to GND while on the board its connected to Vcc. Its like multiple drivers to a pin.. one from internal IO/logic and other externally from Board.