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Hello Alter Gurus;
I am in need of your help. I am trying to configure the settings of WM8731 audio codec found in Altera DE1-SOC using I2C and every try that i made ends up unsuccessful. I do not know why the I2C module that I have written in verilog fails to configure the WM8731. The I2C module in verilog that i used was base on P. Chu book titled "Embedded SoPC design with NIOSII processor and Verilog examples". Any advice and help are greatly appreciated. Kind regards, RyanLink copiado
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Does your I2C module behave exactly as expect when you simulate it?
We can't really second guess what you've written. So, if you want help with code we'll need to see it. However, don't bother posting any code until you can answer 'yes' to the point above. Cheers, Alex- Marcar como novo
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actually yes, i have simulated it using modelsim and it exactly match with standard i2c master waveform. Also the pins are properly assigned. I wonder why i cant configure wm8731
tnx alex- Marcar como novo
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Are you running anything on the HPS? I assume you're not controlling the I2C multiplexer incorrectly? FPGA fabric has control by default.
Try proving your rtl another way. Can you talk to the Video Decoder? The problem with the WM8731 is it's a write only device. So, you can only indirectly confirm it's responding as you want. At least you can read from the Video Decoder. Can you validate your code that way? Read the device identifier from the video decoder(device address: 0x40), register 0x11. You should read 0x1C. Cheers, Alex- Marcar como novo
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If a logic analyzer is available, connect it to the I2C bus and verify the waveforms on the actual hardware. Look not only for I2C protocol conformance, but at the values set to the CODEC. If they are OK, look also at the I2S signals. You may have silence because of problems there. Remember that I2S uses signed not unsigned values.
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Make sure your i2c addressing is correct. Some data sheets give an 8b address (read/write bit in lsb), and peripheral drivers typically want a 7b address (they will set the r/w automatically depending on the transaction).

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