Generating 250MHz clock from Arria V to ADC

[Altera_Forum]

Hi, 

We want to use Altera Arria V(5AGXMB1G4F35C5N) FPGA interfaced with TI ADC ADS6129IRGZ. We are deriving 250 MHz clock required for the ADC using the PLL (ALTPLL core) availale on the device and clock output is sent on the differential clock lines. We have used the output clock as a regional clock (ALTCLKCTRL). Are there any limitations wrt to the clocking scheme described? Is the clocking network described gives proper optimum output skew and SNR?

[Altera_Forum]

--- Quote Start ---  Hi, We want to use Altera Arria V(5AGXMB1G4F35C5N) FPGA interfaced with TI ADC ADS6129IRGZ. We are deriving 250 MHz clock required for the ADC using the PLL (ALTPLL core) availale on the device and clock output is sent on the differential clock lines. We have used the output clock as a regional clock (ALTCLKCTRL). Are there any limitations wrt to the clocking scheme described? Is the clocking network described gives proper optimum output skew and SNR?  --- Quote End ---    as far as I know fpga generated external clocks suffer high jitter and may not be good for ADC clocking. I would rather use a clean external oscillator. check the spec of your ADC clock and fpga jitter figures.

[Altera_Forum]

Yes, I believe kaz is correct. Check the worst case jitter specification for a dedicated PLL output and you'll find it's in the neighborhood of 10% of UI.

[Altera_Forum]

--- Quote Start ---  Yes, I believe kaz is correct. Check the worst case jitter specification for a dedicated PLL output and you'll find it's in the neighborhood of 10% of UI.  --- Quote End ---    Thanks for your reply. I checked for jitter specs, Device specification mentions of a max period jitter of 0.250 ns for Arria V fractional PLLs. Is it recommended to use this as clock for ADC for clock freq 250MHz?  ADC input is a Pulse with different level of amplitudes.  Thanks Ashwini

[Altera_Forum]

--- Quote Start ---  Thanks for your reply. I checked for jitter specs, Device specification mentions of a max period jitter of 0.250 ns for Arria V fractional PLLs. Is it recommended to use this as clock for ADC for clock freq 250MHz?  ADC input is a Pulse with different level of amplitudes.  Thanks Ashwini  --- Quote End ---    What about adc clock jitter requirement. Moreover the adc data and clock to fpga may suffer similar jitter of .25 ns per 4 ns period, pretty tight on fpga timing. You will need to enter clock uncertainty to cover the .25 ns and see report of timing.