Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20803 Discussions

Cannot assign clock signal to XCVR bank pin - Arria 10

New Contributor I

Hello dear community,


I am currently using a Terasic HAN Pilot Plateform (Arria 10) for receiving high speed data from ADC at a rate of 5 Gbps, as well as transmitting the sampling clock of 250 MHz.


Until now, we transmitted signals through FMC connector which works fine. For the future, we want to use the four SFP+ 10Gb transceivers provided by the plateform to receive 5 Gbps data, and send 250 MHz clock.


The issue I face is during compilation time (fitter), showing an incompatibility issue between the clock signal output type from PLL and the xcvr bank of the SFP+.


Actually, from the datasheet, for instance the 1st SFP+ connector transmitter, SFPA_TX_p, is of type "HIGH SPEED DIFFERENTIAL I/O" , and assigned to PIN_AG37. If I assign my clock signal, which is supplied by IOPLL, I get the following error : 


X Error(175020): The Fitter cannot place logic pin in region (0, 61) to (0, 61), to which it is constrained, because there are no valid locations in the region for logic of this type.
X Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
X Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected)


I understand that the PLL output of type GPIO cannot fit with the specs of PIN_AG37 which is from xcvr bank of Arria 10. So is there a way to "convert" or to encode this clock signal so it is understood to be a serial data that can be properly red by SFPA_TX_p ?


For information, I also tried with fPLL, which supplies a "tx_serial_clk", but doesn't seem to work neither.



0 Kudos
6 Replies
Valued Contributor III

If I understand right, you want to send 250 MHz clock through SFP port. That's not directly possible by connecting a PLL, however you generate a bit sequence by oversampling with 500 MHz or 1 GHz clock.

0 Kudos
New Contributor I

Thank you for your response.

Yes I guess this is the way to go, however transceivers in Arria 10 is something pretty new to me and I'm not sure exactly how to take it. Is there a kind of serializer IP in Quartus where I can input my "clock data" ? Is oversampling a common method for this kind of matter ?

0 Kudos
Valued Contributor III
yes, there's a serializer IP. Oversampling is also mentioned in the device handbook for achieving bit rates between 125 and 1000 Mbps.
0 Kudos
New Contributor I

Hello FvM,


I used the "Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP" for generating clock signal, the data part should not be a problem to generate output serialized signal as you mentionned. However it doesn't appear very clear to me what clock(s) I should assign to this IP. Here are some details :





I have to supply 2 clock inputs to the transceiver , and - I suppose - to its CGB, which are :

- tx_serial_clk0

- tx_coreclkin


I saw from the IP datasheet that coreclkin frequency should be  ( Datarate / (parallel_data) )  which is 1GBPS / 8bits = 125 MHz.

It is also mentionned in the picture above that the "TX PLL IP" must provide a clock frequency of 500 MHz related to internal clock division factor. I couldn't find more detail in datasheet to explain if this clock is the serial or core one, which is a bit confusing.


Anyway, the way I assigned clocks, and corresponding to Arria 10 pins, is the following :

- reference_clk from FPGA  core (CLK_50_B2H - 50 MHz) -> IOPLL (125 MHz) -> tx_coreclkin

- reference_clk_from_FPGA core (CLK_50_B3H - 50 MHz) -> fPLL (500 MHz) -> tx_serial_clk0


The compilation fails during fitter. I also used dedicated transceiver reference clock CLKUSR_100 for the fPLL instead of the 50 MHz user clock, and I have in any case same error which is : 


Input port "REFCLK" of "CMU_FPLL_REFCLK_SELECT" cannot connect to PLD port "O" of "IO_INPUT_BUFFER" for node "CLKUSR_100~input".


What is strange is that it shows here an error related to fPLL reference clock, while when I remove the Transceiver IP, the compilation is successful. So I guess it is rather related to Transceiver reference clocking rather than fPLL reference clocking ?


I would be grateful if you could enlighten me on this !





0 Kudos
New Contributor I

Problem solved, on HAN Pilot Plateform, the serial output I use is SFP connector, which also has its dedicated reference clock SFP_REFLCLK_p of 644,53125 MHz.


Thank you for previous answers anyway

0 Kudos


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you

Kshitij Goel

0 Kudos