Cannot generate a bit file for active serial load of Stratix V for cvp init mode

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Cannot generate a bit file for active serial load of Stratix V for cvp init mode

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I am trying to determine the type of bit file needed to program into a serial flash to use for active serial loading of a Stratix V when cvp init mode is used. Convert programming files does not allow selection of the cvp periph and core files when a .rpd output file is selected. Selecting a .rbf file allows generation of the periph and core rbf files, but rbf files are not compatible with active serial mode configuration.

Generation of a .jic file works, but I need a programming file to be loaded onto the serial flash in a running system without a JTAG cable attached. I have a gpio interface to the serial flash to read/write the flash data for in system programming, now I just need to find how the generate the core design file to load into the flash for cvp init mode.

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