Cannot program QSPI memory through ASMI Parallel II IP

[avib]

Hello,

We have a design that connects Avalon-MM Cyclone V Hard IP for PCIe Intel FPGA IP to ASMI Parallel II IP.

The Cyclone V is connected to a QSPI serial Flash memory MT25QL512ABB8ESF (512Mb)

Note that due to the 50MHz maximum clock frequency limitation of the ASMI II IP, we used an Avalon-MM Clock Crossing Bridge between the Avalon-MM Cyclone V Hard IP for PCIe and the ASMI II IP. The PCIe IP works at 125M, and the ASMI II works at 50MHz.

We are able to modify the CSR at address 0x04010000 – 0x040100FF (e.g, perform WR_ENABLE, erase Flash sectors, and more), We are also able to read the Flash memory content.

But we cannot program the Flash data at Addresses 0x00000000 – 0x03FFFFFF.

From the ASMI Parallel II Intel® FPGA IP user guide we understand that, since there are no in-direct registers for address and data like was in the old ASMI IP, in this case in order to modify the Flash memory we should perform direct address-data write transactions, and the ASMI II IP will do the NOR programming sequence .  But, as I wrote, it is not working.

[Wincent_Altera]

Hi,

If you want to be able to access the quad SPI flash that is used to configure the image for the FPGA after the configuration is complete, you can instantiate the alt serial flash module that will allow you to access the FPGA pins connected to the SPI device. I use this block to allow my SPI flash config memory to be accessible via the JTAG chain, but it has capabilities beyond just this function. 

You may refer the user guide below

https://www.intel.com/content/www/us/en/docs/programmable/683299/current/using-the-fpga-serial-flash-loader-ip-85096.html

You want to look at the 'Share ASMI interface in your design' option description.

Regards,

Wincent_Intel

[avib]

Hi Wincent,

First, thank you for your reply!

If we are able to read QSPI memory data content, to erase the Flash, and to RD/WR to/from its status register using the ASMI II registers, isn't it means that the ASMI II IP has granted control on the SPI pins?

Thank you

Avi  

[Wincent_Altera]

Hi Avi,

Once you are able to run the full compilation and perform read/write it shall be okay.

But which SPI control pins that you need to granted to?

Are you able to solve the error that you mention in the first email ?

Regards,

Wincent_Intel

[avib]

Hi Wincent,

We didn't solve the problem yet.
What I meant is that I am not sure that we need to include the Serial Flash Loader IP, since we already able to perform some Flash operations by just using the ASMI II IP, like reading from it, changing its status registers, and even erasing it (what means that the write enable bit was enabled), etc. But direct data write is not working for us. So, the QSPI pins must be toggled by the ASMI II IP during the operations that do work. I assume that the SFL is already embedded in the ASMI II IP.
So, my question was if you still think that we need to include the SFL in our design?

Thank you
Avi

[Wincent_Altera]

Hi Avi,

If the SFL is load and can perform all the needed function (without any error),
you may exclude it from the design.

Let me know if you need any further clarification.
Regards,

Wincent_Intel

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[avib · Accepted solution]

Hi,

We have a FIX! 

We replaced the ASMI II IP with Intel FPGA Generic QUAD SPI Controller II Core, which also supports our specific Flash device, and succeeded to write to the Flash memory.

Thanks

Avi

[Wincent_Altera]

Hi Avi,

Thanks for share with me how you fix this, glad that your problem is solve,

Therefore following our support policy, I have to put this case in close status. 

Hence, This thread will be transitioned to community support.

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel