Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Annunci
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

Carry/Sum Chains

Altera_Forum
Collaboratore onorario II
1.629Visualizzazioni

Hey, 

 

I would like to access the carry-in carry-out logic that is built in to Altera's FPGA LE blocks, via the arithmetic mode.  

 

The Cyclone IV Handbook says that the arithmetic mode is automatically created when the design uses adders and counters. See http://www.altera.com/literature/hb/cyclone-iv/cyclone4-handbook.pdf (http://www.altera.com/literature/hb/cyclone-iv/cyclone4-handbook.pdf) , page 2 - 3. But it also says that the mode can be created manually: 

 

"You can also create special-purpose functions that specify which LE operating mode to use for optimal performance, if required." 

 

When I created a multi-bit adder, the Cin to Cout path was used as the Handbook described. However, it would be nice to be able to set that mode manually, without creating an adder/counter, in order to conserve resources. How could this be done? 

 

Thanks for any help, 

 

Steve
0 Kudos
1 Rispondere
Altera_Forum
Collaboratore onorario II
818Visualizzazioni

There have been various discussions related to implementation of carry chains. A method, that works for sure is based on lcell_comb low-level primitives. 

http://www.alteraforum.com/forum/showthread.php?t=28798
Rispondere