Hello everyone,
I am new to the world of FPGAs, and I need to do a Time to Digital Converter, thus I would need to use a carry chain to precisely mesure time.
I tried a few different things:
- Using the "CARRY_SUM" primitive : I have no idea if I used it right, I basically took 5 of them and connected the cout of one to the cin of the next. It wasn't recognized as a carry chain at all by Quartus
- Using a 4 bit LPM_ADD_SUB: This actually kind of worked, but I would like to convert it to a 1 bit adder, and have 1 adder = 1 ALM, just for things to be easier.
Right now I have created a 1 bit LPM_ADD_SUB, and added it in a VHDL component as follows :
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY carryChainElement IS
PORT (
a,b: IN std_logic;
cin: IN std_logic;
cout: OUT std_logic;
sum: OUT std_logic
);
END carryChainElement;
ARCHITECTURE RTL OF carryChainElement IS
COMPONENT addSub
PORT (
dataa: IN std_logic_vector(0 downto 0);
datab: IN std_logic_vector(0 downto 0);
cin: IN std_logic;
cout: OUT std_logic;
result: OUT std_logic_vector(0 downto 0)
);
END COMPONENT;
BEGIN
addSub1: addSub
PORT MAP (
dataa(0) => a,
datab(0) => b,
cin => cin,
cout => cout,
result(0) => sum
);
END RTL;
Then I added this component to my .bdf file like this (I added the input and output pins because if I put a constant value in a and b, then Quartus would have optimized it away, I also did the same in my other attemps with the CARRY_SUM primitive and the 4 bit adder) :
After the compilation, the chip planner gives me this result :
And finally, the RTL viewer looks like this :
As you can see, Quartus does not recognize it as a carry chain.
I have read the documentation on the Cyclone V, and I understand the concept of ALMs, Arithmetic mode, etc... I just don't know how to actually implement it.
Do anyone have any leads on how I could fix my current attemps with the 1bit adder ?
Thanks a lot,
Benjamin
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Hello,
So here is my RTL view with the 4bit LPM_ADD_SUB,
And here is the chip planner view :
For the RTL view, it looks the same as the 1bit version (with 4 bit instead of 1 obviously), and on the chip planner we can clearly see that the carry chain is used, even though some optimization seems to occur as we only use 3 ALM.
Thank you,
Best regards,
Benjamin
Hi,
example of full adder implemented with lcell_comb wysigwyg primitive can be found in Advanced Synthesis Cookbook, the module is part of basic_adder.v It can be directly used for Cyclone V because Stratix utilizes same 6-input LUT logig cell.
Problem is that cin and cout can't be directly routed to I/O pins, carry chain can only start and end in other logic cells, as gate level logic circuit of full adder shows. When designing with cyclonev_lcell_comb, the interconnect lcells are generated automatically.
Regards
Frank
