Cascading PLLs Cyclone II

[Altera_Forum]

Hey guys, 

 I recently bought a MorphIC-II board that comes with a Cyclone II FPGA (EP2C5F256C8).  I am trying to cascade two PLLs in my design. When I try to compile it I always get this error:  Error (176350): Can't fit fan-out of node pll0:inst_pll0|altpll:altpll_component|_clk1 into a single clock region  I read somewhere else that this FPGA does not allow cascading PLLs. Is that correct? Or am I doing something wrong?  Any help is appreciated. Thanks in advance, Joao

[Altera_Forum]

Looking at the block diagram in: http://www.altera.com/literature/hb/cyc2/cyc2_cii51007.pdf 

 The Cyclone II PLL can only be driven by the one of the four clock input pins that drive that PLL.  So theoretically you can cascade them, but it would require you driving the PLL output pin to the clock input pin of the next PLL.   Some families do have internal PLL cascading, but the Cyclone II is not one of them.  Pete

[Altera_Forum]

Thanks Pete. 

 In my design, I used the two Cyclone II PLLs and connected the output of the first PLL to the input of the second one. The HDL was created through the Megafunctions wizard.  Theoretically, I guess this design should be OK. Am I missing something?  Cheers, Joao

[Altera_Forum]

Yes. The only pins that can drive the PLL are physical pins, there is no internal routing that drives the input to the PLL. 

 So to do this you must drive the clock to a pin (preferably one of the dedicated PLL outputs) the wire it to one of the dedicated inputs of the next PLL.

[Altera_Forum]

Ah OK. That would be my next approach. 

 Thanks for the help. Joao