- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi
I tried to change path name in TimeQuest's Summary. so I used "set_instance_assignment -name" in qsf. Like that. set_instance_assignment -name CLOCK_SETTINGS WR_CLK -to ip_clk # WR_CLK:Clok Setting Name# ip_clk:Clock Node Name Can I convert this restricttion in sdc? It's difficult to read in TimeQuest's Cloks Summary.Link Copied
3 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
There are no .qsf timing settings used by TimeQuest. That setting is for the Classic Timing Analyzer.
My guess is you're using "derive_pll_clocks" which names the PLL outputs with the long hierarchical pin name. Note that you can go to TimeQuest's Info messages at the bottom, and where this assignment is called out, it shows the individual "create_generated_clock" assignments for each PLL output. You can cut and paste these into your .sdc and change the -name option to something more readable. The only major downside with this is that if you change your PLL, you need to manually change these assignments to match them. Personally, I've seen that mistake happen to often and just accept the longer PLL names. (I think Altera plans on having a better workaround for long PLL names someday, but it's something that should have been done years ago...)- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
yes , I use "derive_pll_clocks -create_base_clocks" in sdc. popurse of using is Mega_wizard setting reflect automaticaly in sdc. I hesitated to use "create_generated_clock". and,I want to change more readable any signal in sdc. example is //********************************************************************** 1. set_multicycle_path -end -setup -from [get_keepers {average_calc:average_calc|r_avr_data [*]}] -to [get_keepers {average_calc:average_calc|r_mul_data [*]}] 2 2. set_output_delay -max 2 -clock pll|altpll_component|pll|clk[1] [get_ports out_data [*]] //********************************************************************** How can I make shorter "average_calc:average_calc|r_avr_data [*]" and "pll|altpll_component|pll|clk[1]"?- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
You can use a Tcl variable:
set fast_clk {pll|altpll_component|pll|clk[1]} Then use the variable like so: set_input_delay -clock $fast_clk ... You might have to work with it a little to get wildcards like the average_calc example. Also, for exact names, TimeQuest doesn't need the entity name. Notice that the PLL name doesn't do entity_name:instane|entity_name:instance|... for each hierarchy, and instead just does the instance name between pipes. I don't think you can mix this nomenclature with wildcards though, but not certain.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page