Hello everyone,I'm in the early phases of design for a new board that will use a Cyclone V SE. I'm currently planning my clock domains for the HPS part and I see in several places in the Cyclone V HPS technical reference manual that the SDRAM PLL in the HPS can use three different clock sources: EOSC1, EOSC2, or a user clock from the FPGA (pages 2-3, 2-15, 2-65). Now the problem is that I can't find how I can change this setting in QSys. I've instantiated an altera_hps component, and in the parameters > "HPS clocks", "Output clocks", I can define the clock source for the peripheral pll. In "Input clocks" I can enable or disable the FPGA to HPS Sdram reference clock, but I can't seem to find any setting to choose between ESOC1 or EOSC2. Am I missing something? Where can I define this, or even know if the generated preloader will configure EOSC1 or EOSC2 as source for the Sdram Pll? As a side question, does anyone have experience using a spread spectrum oscillator with a Soc FPGA? Obviously some I/O that require a precise clock frequency, such as Ethernet, can't use it. But what about the rest? Thanks!
It has been brought up in the forum before - I believe the Qsys setting currently does not have a straight forward (i.e. GUI) way to do that. On the other hand, the handbook does provide the register settings on the Clock Manager that seems to be able to do this - albeit in a difficult (need to modify yourself) manner
Silly me... the question has indeed already been asked here (https://www.alteraforum.com/forum/showthread.php?t=53711)...I found the register to modify but I don't like to manually change an automatically generated preloader before compilation... It's the best way to forget it one day. I'll file a service request.