Changing the speedgrade

[Altera_Forum]

Our project is working with EP3C25F324C6 (6nsec). To save money there is a push to change to EP3C25F324C8 (8nsec).  

Will it work? :confused: (Sorry, thats a dumb question, without nearly enough background...)  The existing project doesnt use timing constraints (other than what the mega functions might have), so a recompile will not have enough information for Quartus to tell me if it meats timing, since I have not told Quartus what the necessary timing is.  The project has a few high speed sections - 100mhz ddr, 96 mhz camera and 70 mhz lcd. So timing is not trivial (maybe I should bite the bullet and learn the timing tools, and perhaps floorplaner too :rolleyes: ).  In quartus I changed the device to use the 8nsec part recompiled and loaded it to the 6nsec part. Still works, one old bug came back.  My gues is that there are more surprises in store when actually using the 8nsec device - its not a fair preview to compile for 8nsec and run on 6nsec. (or is it?)  Thank you for your time reading this, and for any insight you may offer. Steve

[Altera_Forum]

(Note that the speed grades don't refer to ns anymore, they're just relative indicators of performance). 

Without timing constraints, how did/do you know the design works in a -6? If it's a valid test, then do the same test on the -8. If it wasn't a valid test, then you don't know about either.  Learning how to do core timing is pretty easy. Take a look at the TimeQuest User Guide I have on alterawiki, and the first chapter is a Getting Started. The I/O constraints are more difficult and take time, but also one of the things that is often likely to fail.

[Altera_Forum]

Hi Rsyc,  

 The TimeQuest user guide looks good, thank you for writing it!  So far the test of the design working is simply to load it to hardware and observe. Doesnt cover variations across temperature or anything like that. Since timming is a certain issue in this design I should invest the time to learn the timing tools.  Thank you, Steve