Programmable Devices

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Programmable Devices

Discussions

Cyclone III: access to the CRC32 register inside the project

can't read/write DDR2 with HPC II

unable to read data on Interrupt

fpga is configured successfully but cannot work

ALT_AVALON_DMA_NSLOTS - how to increase FIFO size for DMA scheduler

Help, search footprint for PLD ACEX EP1K100FC484-1

LPM_ShiftReg block doesn't work?

Cyclone V PLL desired output frequency

Help with my NIOS2 i2C interface

Asynchronous Signal

Error compiling Mega Wizard block!

SPI Master Timing Constraints

Quartus II Crashes

Cyclon IV GX transceiver Starter Kit - PCI Express

Interfacing Cyclone IV FPGA with Marvell PHY 88E1111 using SGMII

Featured Content

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

EPM3064ATC44-7N and EPM3064ATI44-10N

Deserializers in Agilex 3 series

Re: Download speed

Re: Quartus Prime Design Software - JTAG usage