Choosing Cyclone IV device/speed grade

Altera_Forum · ‎03-11-2017

Hi all, I have been developing a system on a DE0-NANO development board (which has a speed grade 6 device) and am now ready to move the design onto a purpose built PCB.

My current HDL design utilizes 1 PLL, 2,595 LE's, 58 Pins, <504Kbit embedded memory, and runs at 200Mhz.

With this in mind, I have been looking at the device ranges;

EP4CE15, as these feature >15,000LE's (room to grow), 4 PLL, 504Kbit embedded memory, and can run at speeds of 200Mhz (according to website).

The thing that's confusing me mostly at the moment, is the speed grade rating of the devices within the EP4CE15 range. It says on the website that they all have a max speed of 200Mhz, which is what I would like my fastest system clock to run at in my design.

The particular device that is appealing due to its price is the EP4CE10E22C8N. Which is speed grade 8, according to the cyclone IV datasheet, the EP4CE10E22C8N's speed grade made's it capable of up to 402Mhz.. which is even more confusing as this is above the quoted 200Mhz max on the website.

I'd be very greatful if someone with a bit of experience could step in and let me know what's what, In as close to plain English as possible! I have tight deadlines as this is part of a bigger project that makes up my final project for undergrad degree, so I really need things to go as smoothly as possible! Any additional advice on choosing an appropriate device is welcome, if there is anything that I have obviously not considered/need to check.

Thanks, Chris.

Altera_Forum · ‎03-11-2017

So far I have learned that I must 'define' my clock signals using an .SDC file, which I have done successfully, using the following script;

# Base clock

create_clock -name {CLOCK_50} -period 20 [get_ports {CLOCK_50}]

# Clocks derivied from base clock

derive_pll_clocks

derive_clock_uncertainty

I no longer receive any error messages about my undefined clock signals.

Initially, after setting up my clocks in the .SDC file I received critical errors stating 'timing constraints not met'. But by reducing my system clock down from 200Mhz to 100Mhz (200Mhz was really not required). These critical errors have gone.

However, although the clocks are resolved (as far as I can see), I still have many unconstrained paths;

http://i64.tinypic.com/6p8137.jpg

I'm currently trying to gain a better understanding in order to understand resolve these issues. It's my hope that one of the tech guys at uni will be able to help.. though its no secret that they all dislike and lack experience with FPGA, for some reason.

EDIT: Ultimately, as the FPGA is only part of my project, I just need to get to the point where I can settle on a chip for my design as quick as possible. My design runs works on the De0-Nano, I just need to be sure I can move from to another device within the same family (Cyclone IV E), and be confident that moving from a speed grade 6 device to 7 or possibly 8 will not result in failure. I have researched and become familiar with EPCS (serial configuration IC), so I have a method to remotely configure the FPGA, but before I can begin investigating PCB layouts and circuit considerations I must, obviously, settle on a device.

Altera_Forum · ‎03-13-2017

Hi, from what I see online, the 402Mhz speed is mentioned on some of the distributor's website, but Altera's website did not mention the FMax (core performance) for these chips. Which makes sense, since the Core FMax depends on various factors such as the complexity of routing, available resource, etc.

If you would like to know whether slower chips (such as speed grade 8) will work with your design, try selecting them in Quartus and compile your design again. If you do not encounter any timing error (assuming of course, that you have constrained them properly) then the chip should work.

So far, I've only run up to 100-120Mhz on these Cyclone IV E chips... (with Nios)

Altera_Forum · ‎03-13-2017

--- Quote Start ---

Hi, from what I see online, the 402Mhz speed is mentioned on some of the distributor's website, but Altera's website did not mention the FMax (core performance) for these chips. Which makes sense, since the Core FMax depends on various factors such as the complexity of routing, available resource, etc.

If you would like to know whether slower chips (such as speed grade 8) will work with your design, try selecting them in Quartus and compile your design again. If you do not encounter any timing error (assuming of course, that you have constrained them properly) then the chip should work.

So far, I've only run up to 100-120Mhz on these Cyclone IV E chips... (with Nios)

--- Quote End ---

Thanks for the reply. I have spoken to one of the guys at university and been told that in order to constrain my design I must start by defining all the external signal inputs to the FPGA. I'm working on this now, though I have to admit I'm not completely sure where to start.

I have data coming into the FPGA from an audio codec, and SPI line from a micro-controller. It is my understanding, that it is these signals that need to be constrained.

EDIT: For example, my SPI input from the micro-controller consists of three data lines; SCK, S_IN, SS, its just a simple slave peripheral. I have passed all these signals through flip-flop synchronizers, as I understand is required in order to synchronize to my system clock such that I can sample those signals on the rising edge of my system clock. If anyone could talk me though, or give advice on how to constrain these inputs it would be a HUGE help.

In fact, to begin with, I would appreciate it if someone could confirm that I have constrained my clocks correctly. In my design, I have an input pin 'CLOCK_50' which is tied to the 50Mhz clock of the De0-Nano, which is used as an input to a PLL megafunction which then outputs 'sys_clock', which is at 100Mhz. This is illustrated in the image below.

It is my understanding, that these are the only clocks that need to be constrained, since all inputs to the FPGA are synchronzed to and sampled on the rising edge of 'sys_clock'.

The code below is what I have used in my .SDC file to constrain these clocks, it is my understanding that this is sufficient.

#Base clock
create_clock -name {CLOCK_50} -period 20 
# Clocks derivied from base clock
derive_pll_clocks
derive_clock_uncertainty

http://i68.tinypic.com/11aeurd.jpg

Cheers, Chris.

Altera_Forum · ‎03-14-2017

I have not worked with SPI previously, but I guess it shouldn't be too different from the ones below:

http://www.alterawiki.com/wiki/timing_constraints

Constrain SPI core example:

http://www.alterawiki.com/wiki/constrain_spi_core

Regarding your .sdc file, I believe it is sufficient for the clocks within the system. I would be interested to hear from other developers on this forum as well :)

Altera_Forum · ‎03-17-2017