When an interrupt is signalled on a PCIe IRQ line from my Qsys component, I can see the interrupt status bit being asserted at address 0x0040 in the PCIe CRA slave. I then acknowledge the interrupt on the actual component (to de-assert the IRQ), but I find that I also have to clear the bit in the status register at address 0x0040 in the CRA slave. As I understand it (from reading the manual), the latter step should only be necessary for mailbox interrupts but NOT for MM IRQ interrupts.
Any experts here able to provide clarification?
BTW I am testing this in System Console using a JTAG to Avalon Master component attached to the PCIe CRA slave.
I am afraid the question/help requested here is not clear. Are you asking on whether the step to clear the bit at address 0x00040 in the CRA slave compulsory for MM IRQ interrupts?
Also please let me know if you are using "AVMM Hard IP +" or "AVMM Hard IP" or "AVST" as the PCIe IP in Quartus.