Hello, I noticed that the newer FPGA's (Cyclone 10, Arria 10, Stratix 10) do not support 3.3V LVCMOS only 3V IO. Doesn't this limit the number of devices that you can interface with and why did Intel choose 3V IO?
I think we are seeing the beginning of the trend to lower power from 3.3V devices to 2.5V just as we saw the 5V devices move down to the 3.3V devices. Xilinx FPGAs, even the newer ones, still support 3.3V devices. Xilinx FPGAs have High-range pins (1.2V to 3.3V) IO and High-performance pins (1.2V to 1.8V) IO.