Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

Clock Assingment

Altera_Forum
Honored Contributor II
1,254 Views

Hi! I am currently trying to assign one of the ClockControl blocks in my design. In Chip planner I have founded current Clock Control block and his full name: |Test1|ClockSource:U3|altpll:altpll_component|ClockSource_altpll:auto_generated|wire_pll1_clk[1]~clkctrl. When I copy this name in window for assignments block is not recognized? I am really struggling with this so any help is welcome. Also I have tried to move Clock control block with drag and move method but when I have positioned block in wanted position action was cancelled for some reason. Maybe CLKCTRL blocks are dedicated to PLL?

0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
539 Views

I'm guessing you don't need the ~clkctrl block, as that's the output of the global driver. If I have trouble assigning names, I make a copy of the project with database and go to Assignments -> Back-Annotate and lock it down that way. You can also use the script here: 

http://www.alterawiki.com/wiki/back_annotation_script 

To do a more controlled back-annotation. I've often changed the location search string to *CLKCTRL* to lock down all the clkctrl globals. This method ensures you get the right name and format.
0 Kudos
Altera_Forum
Honored Contributor II
539 Views

Thank you for this useful informations !

0 Kudos
Reply