Variable does not increment

Altera_Forum · ‎04-24-2016

I don't know why the variable clk_count does not increments, it's steel il the value 1. There is the code


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
Entity TestVar Is
Port (
        CLK      : in std_logic;
        RST      : in std_logic
      );
end TestVar;
ARCHITECTURE Arch OF TestVar Is
TYPE State_Type IS (Power_Up);
Signal pr_Stat, nx_Stat : State_Type;
Begin
 
PROCESS(CLK, RST)
BEGIN
  IF(RST = '1')THEN
      
      pr_Stat <= Power_Up;
  ELSIF(Clk'EVENT and Clk = '1') THEN
          pr_Stat <= nx_Stat;
          
  END IF;
END PROCESS;
PROCESS(pr_Stat)
    VARIABLE clk_count : INTEGER RANGE 0 TO 4194304 := 0;
BEGIN
    CASE pr_Stat IS
    
    When Power_Up =>
          IF(clk_count < 50) THEN
            clk_count := clk_count + 1;
            nx_Stat <= Power_Up;
             ELSE
                clk_count := 0;
          END IF;
            
    When OTHERS => NULL;
      END CASE;
END PROCESS;
END Arch;

Altera_Forum · ‎04-24-2016

Because pr_stat signal only has 1 state. It increments clk_count to 1 at time 0 and then because there are no more events on pr_stat, it can never increment again.

Counters should not be in unclocked processes.

Altera_Forum · ‎04-24-2016

I think that the process(pr_stat) is executed every rising edge of clock. So the counter have to be incremented every rising edge.

Altera_Forum · ‎04-25-2016

pr_stat is executed every rising edge, however, it values remain unchanged. Therefore the clk_count process that depends on pr_stat changes will never get incremented. The PROCESS statement is the sensitivity list for the clk_count.

Altera_Forum · ‎04-25-2016

--- Quote Start ---

I think that the process(pr_stat) is executed every rising edge of clock. So the counter have to be incremented every rising edge.

--- Quote End ---

But it isnt, because you didnt make it a clocked process. This process will only execute when pr_stat changes, and because it never changes, the counter will get the initial increment at time 0 and then never do anything again.

Make the process sensitive to the clock and make the process use the clock to make the counter increment. If you do not add if rising_edge(clk) to the process, the hardware hehaviour will not match the simulation.

Altera_Forum · ‎04-25-2016

Thank You, I did one process including the clock and it work. The thread can be closed.