Hello friends,
I have a question regarding the delaying of a clock signal inside an Altera and how one would go about performing this. I preface this question with the statement that I probably do not know enough about timing constraints, so if there is an easy way to do this I apologize. Please help a newbie out!
I'm implementing an RGMII PHY interface and it calls for the delaying of the clock by a fraction of a clock time (~1.5ns to 2ns). I know that some PHYs can do this timing skew internally, but I'd like to implement it in the Altera for various reasons. I think that Xilinx has an IODELAY call that essentially does this.
How do I accomplish this in an Altera? Best I can tell, Altera doesn't have anything like IODELAY (unless it's some abstract assignment in the assignment editor that I've overlooked). Can this be done using certain timing constraints?
Thank you for your help!
