Clock out from GX Transciever

Altera_Forum · ‎03-11-2016

I'm planning on sending two lanes of JESD204B data down a QSFP cable. By my understanding this should be quite possible as there are four CML lanes in one direction which is enough for the two data lanes, and the devclk/sysref signals.

On the dev kit I am using (Stratix V GS DSP Development Kit) there is a QSFP connector which is wired up directly to the high speed transceivers of the FPGA, which means I need to use those to output the JESD data (easy) but also the devclk/sysref.

I am aware that I can use on of the transceivers as a clock input, but I am curious if I can use them as clock outputs. I couldn't find anywhere that specifically states this is possible. I think it should be, after all a clock is basically just alternating data.

Would it just be a case of feeding out the clock signal from the top level of the design and assigning it to the transceiver pins? Or would I need to instantiate high speed transceivers to send out the clock?

I tried the first option (just assigning to transceiver pins), but as expected, this didn't work - the fitter gave the following error:

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Error (184016): There were not enough differential output pin locations available (1 location affected)

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Altera_Forum · ‎03-11-2016

Never tried it, but it might be possible if you pick the transceiver that has the CMU PLL in it (if the Stratix V transceiver architecture at all resembles the Cyclone V architecture). Otherwise you'd end up having to generate a custom high speed transceiver to output the clock, which again should be possible, but much more of a pain.

Altera_Forum · ‎03-18-2016

Surely somebody has needed to do this?