Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,489 Views

Closing timing when extra levels of combinatorial logic is small inside of adder IP

I am trying to close timing using the Quartus Timing Analyzer recommendations. Unfortunately, it appears that there is always 1 additional level of combinatorial logic and this level always seems to occur inside of a megafunction such as LPM_ADD_SUB. 

 

Here is an example of the recommendation given to me in the Recommendations Summary. Note that the difficulty is associated with registers that I have no control over within my Verilog code. What do I have to do to close timing? What is the OTERM1555 register (or similar)? Let me know if any further information is required. The timing is -7.417 ns slack. 

 

Reduce the levels of combinational logic for the path from registers:registe...irp_gen|a_add[6] (about:blank#) to registers:registe...5]~286_oterm1555 (about:blank#) [hide details] (about:blank#) 

  • issue: long combinational path (rdb:long%20combinational%20path) 

  • from: registers:registers|signal_production:signal_production|chirp_gen:chirp_gen|a_add
  • to: registers:registers|signal_production:signal_production|chirp_gen:chirp_gen|add_sub2:add_sub2|lpm_add_sub:LPM_ADD_SUB_component|add_sub_foj:auto_generated|pipeline_dffe
  • timequest analysis: }%20-to%20{registers:registers|signal_production:signal_production|chirp_gen:chirp_gen|add_sub2:add_sub2|lpm_add_sub:lpm_add_sub_component|add_sub_foj:auto_generated|pipeline_dffe
  • extra levels of combinational logic: 

 

0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
120 Views

Quartus allows you add pipeline registers inside their modules (though this increases latency)

Altera_Forum
Honored Contributor I
120 Views

Thanks, kaz. Is this a timing recommendation that can be safety ignored, or is there a way to add additional pipeline registers inside of each IP module? I am assuming that I simply need to increase the pipeline latency when configuring the IP? Essentially, I still need to pipeline the calculation?

Altera_Forum
Honored Contributor I
120 Views

I managed to close timing by writing a Verilog module performing 128 bit addition using 64-bit numbers. Each 128 bit number was split up into high and low 64-bit numbers. The high and low parts were added, and a carry bit added for overflow. This worked well and the timing recommendation went away. I had to create an instance of LPM_ADD_SUB where the operation is piplined over a number of clock cycles. The pipelining was added when an instance of the megafunction was created. The pipeline is added when using the GUI in Quartus to create an instance of the LPM_ADD_SUB.