Combining Intel IP with custom HDL

[Damian]

I have some custom-coded VHDL components that I want to combine with Intel IP (DDR Controller & NIOS processor).  How do I do this?  I've scoured the documentation and videos and am still unclear.  I know how to create a custom VHDL project in Quartus and how to create a system in Platform Designer, but I can't seem to figure out how to integrate IP with custom HDL.

[RichardTanSY_Intel]

Hi @Damian ,

I am not familiar with the DDR and NIOS IP, and if you want merge/modify/integrate IP with custom HDL. 

You can generate the IP design files (generate HDL with your preferable language) and integrate the custom code into the IP generated synthesis file. 

Do note, we do not support any customize IP. You will need to solve any error/failure that occur by your own.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

[Damian]

I figured out how to do it by trial and error and by studying generated artifact files in Platform Designer.  In the end I was able to create a system design in Platform Designer that connects Intel IP modules with my own custom VHDL modules.  This is how I did it:

I clicked "New Component" in the IP Catalog tab for each custom component I wanted to instantiate at the same level as the NIOS and the DDR emif components to connect to them.  When the Component Editor opened, I used the Files tab to specify all the VHDL files of my custom-coded module.  Then I manually created interface and signals in the Signals & Interfaces tab (Signals are defined per interface).  There are many types of interfaces from which to chose, clocks, resets, avalon busses, etc.  For any of my own interface types that didn't fit any of the pre-defined types, like some arbitrary  std_logic_vector port in my top level, I used the "Conduit" type (Conduit is a catch all).  You can group more than one signal under any interface, for instance, since all my register_write signals were going to be passed as a group between modules, I just created a Conduit Interface called "Register_write" and then within that interface I created signals that were named the ports on my top level that corresponded to the register write function.  When you click Finish, Platform Designer generates a *_.tcl file that specifies your signal settings.  I learned the syntax of that file by trial and error and was able to speed things up by just editing that file instead of using the GUI.  When you edit the file, once you re-open that component in the IP Catalog tab (Right-click the component and click Edit...) the signals you created in the _hw.tcl file will show up in the GUI (unless you made a mistake in the syntax).  Then you can add that component to the System View and connect the ports on it to the Intel IP like NIOS and DDR emif.  As you would guess, the interfaces have to match properly to avoid errors or even make connections possible between components (for example, you won't even be able to connect a Reset to a Clock).  Some interfaces will connect, but if there are mismatches between the interfaces (say, one interface is missing a signal the other one has) you'll get error in the System Messages tab.  You can add and remove interface and signals as needed by just right-clicking your custom component in the IP Catalog tab and clicking "Edit... ".

Note: You can do the above process even before you have any custom VHDL made yet.  In that case you will (obviously) skip specifying the VHDL files and just create interfaces/signals in the Interface & Signals tab.  Then go back to the Files tab and use the "Generate HDL" button.  This will created a top level VHDL file with ports that match the interfaces and signals you created.

A word of explanation about interfaces and signals.  Every signal in an interface will have a Signal Type specified.  Pre-defined interfaces have signal types like "address" and "readdatavalid".  When you create a custom interface (conduit), the signals within that interface will each need to have a signal type assigned.  Platform Designer will initially autopopulate a value, but you can rename it.  One important thing is that signal types within an interface must be a unique name within that interface.  This is because when you later connect that interface to the interface on another component (custom or not), the signal types have to match or you will get an error message.  That is the case if you have an extra signal in one of the components' interfaces or even if you have the correct number of signals but one of the signals has a different type (like a typo).  There are some other properties that have to be set correctly, like Input/Output, otherwise you'll get errors (for instance, if you try to connect an output to an output).  The error messages are very helpful to work through the sometimes detail-oriented task of getting all the interfaces and signals correct.

[Damian]

I have to add this warning: be very careful when you manually edit the _hw.tcl files.  I kept having a problem where Quartus just would not recognize the IP that I had edited.  I finally concluded that it was because I had manually added a bunch of signals to that IP by editing the .tcl file instead of using the tedious GUI.  I would restrict editing that file to changing a typo or fixing an incorrect case (the signals and types are case sensitive -- ugh).  I guess there's a reason the top of the file says "DO NOT MODIFY".  Hold my beer...

[RichardTanSY_Intel]

I have yet to receive any response from you to the previous question/reply/answer that I have provided but I believed that I have answered your question. 
With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.