Error (275021): Illegal wire or bus name " " of type signal
Error (12153): Can't elaborate top-level user hierarchy
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 2 warnings
Can anyone please help me understand what exactly I should do to rectify it?
Check the connections of clock,wren(need to be wire) of ram instance & PRN, CLRN should connect inputs using pin tool.
please let me know if you have any different concern.
Just to explain a bit clearer, you have clock and wren connected as busses (thick lines) instead of individual wires (thin lines). Delete the busses and use the wire tool to make the connections. Also, the reset input into the register (CLRN) should be hooked up as well, either to an I/O pin or perhaps even just pulled high.