I have two almost identical projects in Quartus.
The first project compiled for 10 minutes, the second - for two hours.
The project compiled for two hours has info
Info (188005): Design requires adding a large amount of routing delay for some signals to meet hold time requirements, and there is an excessive demand for the available routing resources. The Fitter is reducing the routing delays of some signals to help the routing algorithm converge, but doing so may cause hold time failures. For more information, refer to the "Estimated Delay Added for Hold Timing" section in the Fitter report.
But how can I see form the report what is the problem?
The problem is - when I clock different components from different clock domains - it takes for hours to synchronize.
How can I inhibit the clock synchronization in Quartus?
put in more register in btw the components for synchronization, make sure you check your functionality after doing that.
If those diff clock domain are not important for functionality, set false path.