Hi all,
I want to use a qsys file that is mostly a copy of a previous version of the same project. I have a design that I can synthesize and implement on an Arria10 FPGA but due to obsolescence of a memory component I had to modify my design accordingly. So I have copied the qsys file (and stored it in another directory than my workspace for a backup) and renamed it. Then I opened the new qsys file in Platform Designer (I'm using Quartus 17.1 Standard version btw) and changed the ddr4 settings of the project and then generated HDL (ended with no errors). Then I compiled my design and got an error message regarding the EMIF IP's that's generated by Altera considering my qsys file. I got the following error message but not sure what's wrong here.
Any help would be appreciated!
Cheers,
Info (332104): Reading SDC File: 'max_SOM12/altera_emif_arch_nf_171/synth/max_SOM12_altera_emif_arch_nf_171_lgjq4ha.sdc'
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Critical Warning: get_entity_instances : Could not find any instances of entity max_SOM12_altera_emif_arch_nf_171_lgjq4ha
Error: The auto-constraining script was not able to detect any instance for core < max_SOM12_altera_emif_arch_nf_171_lgjq4ha >
Error: Make sure the core < max_SOM12_altera_emif_arch_nf_171_lgjq4ha > is instantiated within another component (wrapper)
Error: and it's not the top-level for your project
Critical Warning (332008): Read_sdc failed due to errors in the SDC file
