Honored Contributor II
01-05-2018 06:17 PM
My design is based on a FPGA online course I'm taking through CourseseaI'm seeing a conflict between the compile error and the pin planner I'm using Quartus 16.1 lite (free), processor MAX10 10M08DAF484C8GES I did research the forum for help, no luck. I'm also the Max10 datasheets compile error states 37 pins assigned in I/O bank 8 only 36 I/O pins allowed versus pin planner shows 33 pins assigned and 3 pins available, see IO Bank Usage attachment Per the instructor direction I assigned the pins from a combination of - pin planner:
- 2 single pins dropped
- dropping grouped bus pins into the bank#
- other single pins.