- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
When using SPI communication, where a CPLD is acting as the slave and a microcontroller is the master, would the SPI clock (SCK) be connected to a global clock network of the CPLD? I.e. one of the CLK ports (labelled with a falling edge in the Quartus pin planner) ?
Link Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
It can be, yes. However, it doesn't have to be - you could use an ordinary I/O pin instead.
What is best for your design depends on what you're expecting to do with your slave CPLD. Cheers, Alex
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page