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External SPI master clock connect to CPLD global clock network ?

Altera_Forum
Honored Contributor II
862 Views

When using SPI communication, where a CPLD is acting as the slave and a microcontroller is the master, would the SPI clock (SCK) be connected to a global clock network of the CPLD? I.e. one of the CLK ports (labelled with a falling edge in the Quartus pin planner) ?

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Altera_Forum
Honored Contributor II
92 Views

It can be, yes. However, it doesn't have to be - you could use an ordinary I/O pin instead. 

 

What is best for your design depends on what you're expecting to do with your slave CPLD. 

 

Cheers, 

Alex
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