When you generate a system with QSYS, the generator does not check the VHDL code completely.
Then, when you include the generated system into your project, first you have to run the analysis and synthesis.
Generally the compiler stops after the first, or, if you are lucky, after three or four errors. So, if you have built a BIG system, containing many VHDL sources, to reach the end of the analysis and synthesis, you have to:
1) Modify the failed source, but NOT the one that opens double-clicking the error description (this one is the copy of your source file located in the QSYS folder... so if you do this at the next QSYS generation you will lose the modified sources and the errors that you have corrected once will return back). You have to open your original source file and fix the error.
2) Rebuild the QSYS
3) restart the analysis and synthesis, hoping this is the last error. If not you have to restart the process.
With a small QSYS system, or with a system made mainly of Altera-provided IPs (processors, memory controller, etc...) this could be a small problem. But with a large QSYS system, made of many custom blocks, this is a nightmare, because the first analysis and synthesis could take many hours :mad:
What to do? Is it planned to solve this issue?
regards
Davide Camerano
