Complete Solution - how to JTAG program

[Altera_Forum]

Here is a complete description as to how to program a Cyclone II or III FPGA via the JTAG interface. I've used this process to JTAG program one FPGA from another and also program an FPGA from a microprocessor. 

 The solution alos enables you to JTAG program an FGPA that has a blank EPCS** chip attached.   The following steps can be implemented in C code or Verilog.    Firstly use Quartus to create an UNCOMPRESSED *.rbf file of the image you wish to load into the target FPGA.   For a Cylone II remove the first 44 bytes of the *.rbf file. For a Cyclone III add 16 bytes of 0xFF to the end of the file. You could do these steps in your Verilog or C code but since I was using a PC to program my FPGA is was easier to do the file preparation on the PC.   Then implement the following in your microprocessor or FPGA.   Firstly, you need to check that you can see your target FPGA on the JTAG bus and that it identifies correctly. I only had one device on the chain but you could extend to multiple devices.   Get Device ID - Sequence is as follows:    Reset JTAG chain TMS = 1,1,1,1,1 Goto Shift-DR TMS = 0,1,0,0 Toggle TCK 32 times and read TDO into a shift register following the negative edge of TCK   Let's look at the first line, Reset JTAG chain. You set TMS = 1 and then toggle TCK from 0 to 1 and back to 0. Do this 5 times.    You then move to Shift-RD state like this:   set TMS = 0,  toggle TCK set TMS = 1 toggle TCK set TMS = 0 toggle TCK set TMS = 0 toggle TCK    then toggle TCK 32 times and on the negative edge (i.e. 1 to 0) load TDO into a shift register. After the 32nd clock the shift register will contain 32 bits that correspond to the IDCODE of the target FPGA. If the shift register contains all 0's then the JTAG chain in broken!    You can find the IDCODE for a particular FPGA by looking in the relevant *.BSD file. For example for an EP3C25Q240 look here.    ftp://ftp.altera.com/outgoing/download/bsdl/ep3c25q240.bsd   The value you read from the shift register may not be in the same bit order - I leave that as an exercise for the reader!   Once you can read the correct IDCODE you are ready to program the target FPGA.    FPGA program code - Sequence is as follows:     Reset JTAG chain TMS = 1,1,1,1,1 Goto Shift-IR TMS = 0,1,1,0,0 TDI = ACTIVE_DISENGAGE* (shift 10 bits, LSB first), set TMS high on 10th bit Goto Update-IR TMS = 1  Reset JTAG chain TMS = 1,1,1,1,1 Goto Shift-IR TMS = 0,1,1,0,0 Select program mode TDI = 0x002 ( shift 10 bits, LSB first), set TMS high on 10th bit Goto Update-IR TMS = 1 Set TDI high TDI = 1 Goto Shift_DR TMS = 1,0,0 Shift in 3181 1's TDI = 1 (for Cyclone III, use 300 for Cyclone II) Shift in rbf file to TDI (LSB first) (for Cyclone II only skip the first 44 bytes of the file if not already removed when preparing rbf file) At end of file clock in 128 1's (16 x 0xFF) on TDI line (for Cyclone III only if not already added when preparing rbf file) Goto Update-DR TMS = 1,1 Goto Run-Test/Idle TMS = 0 Reset JTAG chain TMS = 1,1,1,1,1  Goto Shift-IR TMS = 0,1,1,0,0 Select Startup mode TDI = 0x003 (shift 10 bits, LSB first), set TMS high on 10th bit Goto Update-IR TMS = 1 Run - Test/Idle TMS = 0 Toggle TCK 200 times Reset JTAG chain TMS = 1,1,1,1,1   * ACTIVE_DISENGAGE = 10'b1011010000 for Cyclone III and 10'b0000001101 for Cyclone II This is the trick that enables a JTAG load of an FPGA that has an erased EPCS** attached.   I'm working on code that will program an EPCS** attached to a Cyclone II or III via the JTAG pins. I have a problem using some of the JTAG pins on the FPGA to do this so will need the help of an Altera Guru before I can post the solution.    Hope this helps someone.